Texas Instruments Dual-Single Socket CardBus and UntraMedia Controller PCI7621 User Manual

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3.8.9PCI Power Management

3.8.9.1 CardBus Power Management (Functions 0 and 1)

The PCI Bus Power Management Interface Specification for PCI to CardBus Bridgesestablishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of seven power-management states, resulting in varying levels of power savings.

The seven power-managementstates of PCI functions are:

D0-uninitialized− Before controller configuration, controller not fully functional

D0-active− Fully functional state

D1 − Low-powerstate

D2 − Low-powerstate

D3hot Low-powerstate. Transition state before D3cold

D3cold − PMEsignal-generationcapable. Main power is removed and VAUX is available.

D3off − No power and completely nonfunctional

NOTE 1: In the D0-uninitializedstate, the PCI7x21/PCI7x11 controller does not generate PME and/or interrupts. When bits 0 (IO_EN) and 1 (MEM_EN) of the command register (PCI offset 04h, see Section 4.4) are both set, the PCI7x21/PCI7x11 controller switches the state toD0-active.Transition from D3cold to theD0-uninitializedstate happens at the deassertion of PRST. The assertion of GRST forces the controller to theD0-uninitializedstate immediately.

NOTE 2: The PWR_STATE bits (bits 1−0) of the power-managementcontrol/status register (PCI offset A4h, see Section 4.44) only code for four power states, D0, D1, D2, and D3hot. The differences between the three D3 states is invisible to the software because the controller is not accessible in the D3cold or D3off state.

Similarly, bus power states of the PCI bus are B0−B3. The bus power states B0−B3 are derived from the device power state of the originating bridge device.

For the operating system (OS) to manage the controller power states on the PCI bus, the PCI function must support four power-managementoperations. These operations are:

Capabilities reporting

Power status reporting

Setting the power state

System wake-up

The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 (CAPLIST) of the status register (PCI offset 06h, see Section 4.5).

The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI7x21/PCI7x11 controller, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, then the next item pointer must be set to 0. The registers following the next item pointer are specific to the capability of the function. The PCI power-managementcapability implements the register block outlined in Table 3−15.

Table 3−15. Power-ManagementRegisters

 

REGISTER NAME

 

 

OFFSET

 

 

 

 

 

 

Power-managementcapabilities

Next item pointer

Capability ID

A0h

 

 

 

 

 

Data

Power-managementcontrol/status register bridge support extensions

Power-managementcontrol/status (CSR)

A4h

The power-managementcapabilities register (PCI offset A2h, see Section 4.43) provides information on the capabilities of the function related to power management. Thepower-managementcontrol/status register (PCI offset A4h, see Section 4.44) enables control ofpower-managementstates and enables/monitorspower-managementevents. The data register is an optional register that can provide dynamic data.

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For more information on PCI power management, see the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges.

3.8.9.2 OHCI 1394 (Function 2) Power Management

The PCI7x21/PCI7x11 controller complies with the PCI Bus Power Management Interface Specification. The controller supports the D0 (unitialized), D0 (active), D1, D2, and D3 power states as defined by the power management definition in the1394 Open Host Controller Interface Specification, Appendix A4.

Table 3−16. Function 2 Power-ManagementRegisters

 

REGISTER NAME

 

 

OFFSET

 

 

 

 

 

 

Power-managementcapabilities

Next item pointer

Capability ID

44h

 

 

 

 

 

Data

Power-managementcontrol/status register bridge support extensions

Power-managementcontrol/status (CSR)

48h

3.8.9.3 Flash Media (Function 3) Power Management

The PCI Bus Power Management Interface Specification is applicable for the flash media dedicated sockets. This function supports the D0 and D3 power states.

Table 3−17. Function 3 Power-ManagementRegisters

 

REGISTER NAME

 

 

OFFSET

 

 

 

 

 

 

Power-managementcapabilities

Next item pointer

Capability ID

44h

 

 

 

 

 

Data

Power-managementcontrol/status register bridge support extensions

Power-managementcontrol/status (CSR)

48h

3.8.9.4 SD Host (Function 4) Power Management

The PCI Bus Power Management Interface Specification is applicable for the SD host dedicated sockets. This function supports the D0 and D3 power states.

Table 3−18. Function 4 Power-ManagementRegisters

 

REGISTER NAME

 

 

OFFSET

 

 

 

 

 

 

Power-managementcapabilities

Next item pointer

Capability ID

80h

 

 

 

 

 

Data

Power-managementcontrol/status register bridge support extensions

Power-managementcontrol/status (CSR)

84h

3.8.9.5 Smart Card (Function 5) Power Management

The PCI Bus Power Management Interface Specification is applicable for the Smart Card dedicated sockets. This function supports the D0 and D3 power states.

Table 3−19. Function 5 Power-ManagementRegisters

 

 

REGISTER NAME

 

 

OFFSET

 

 

 

 

 

 

 

 

Power-managementcapabilities

Next item pointer

Capability ID

44h

 

 

 

 

 

 

Data

 

Power-managementcontrol/status register bridge support extensions

Power-managementcontrol/status (CSR)

48h

3.8.10

CardBus Bridge Power Management

 

 

 

The PCI Bus Power Management Interface Specification for PCI to CardBus Bridgeswas approved by PCMCIA in December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power Management Interface Specificationpublished by the PCI Special Interest Group (SIG). The main issue addressed in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridgesis wake-up from D3hot or D3cold

without losing wake-upcontext (also called PME context).

The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridgesfor D3 wake-up are as follows:

Preservation of device context. The specification states that a reset must occur during the transition from D3 to D0. Some method to preserve wake-upcontext must be implemented so that the reset does not clear the PME context registers.

Power source in D3cold ifwake-upsupport is required from this state.

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The Texas Instruments PCI7x21/PCI7x11 controller addresses these D3 wake-upissues in the following manner:

Two resets are provided to handle preservation of PME context bits:

Global reset (GRST ) is used only on the initial boot up of the system after power up. It places the PCI7x21/PCI7x11 controller in its default state and requires BIOS to configure the controller before becoming fully functional.

PCI reset (PRST ) has dual functionality based on whether PME is enabled or not. If PME is enabled, then PME context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset. Please see the master list of PME context bits in Section 3.8.12.

Power source in D3cold ifwake-upsupport is required from this state. Since VCC is removed in D3cold, an auxiliary power source must be supplied to the PCI7x21/PCI7x11 VCC terminals. Consult thePCI14xx Implementation Guide for D3 Wake-Up or thePCI Power Management Interface Specification for PCI to CardBus Bridges for further information.

3.8.11 ACPI Support

The Advanced Configuration and Power Interface (ACPI) Specificationprovides a mechanism that allows unique pieces of hardware to be described to the ACPI driver. The PCI7x21/PCI7x11 controller offers a generic interface that is compliant with ACPI design rules.

Two doublewords of general-purposeACPI programming bits reside in PCI7x21/PCI7x11 PCI configuration space at offset 88h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event status and enable bits reside in thegeneral-purposeevent status register (PCI offset 88h, see Section 4.32) andgeneral-purposeevent enable register (PCI offset 89h, see Section 4.33). The status and enable bits are implemented as defined by ACPI and illustrated in Figure 3−16.

Status Bit

Event Input

Event Output

Enable Bit

Figure 3−16. Block Diagram of a Status/Enable Cell

The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the pending status bit. The control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. A hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report events.

For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification.

3.8.12 Master List of PME Context Bits and Global Reset-OnlyBits

PME context bit means that the bit is cleared only by the assertion of GRST when the PME enable bit, bit 8 of the power management control/status register (PCI offset A4h, see Section 4.44) is set. If PME is not enabled, then these bits are cleared when either PRST or GRST is asserted.

The PME context bits (functions 0 and 1) are:

Bridge control register (PCI offset 3Eh, see Section 4.25): bit 6

System control register (PCI offset 80h, see Section 4.29): bits 10−8

Power management control/status register (PCI offset A4h, see Section 4.44): bit 15

ExCA power control register (ExCA 802h/842h, see Section 5.3): bits 7, 5 (82365SL mode only), 4, 3, 1, 0

ExCA interrupt and general control (ExCA 803h/843h, see Section 5.4): bits 6, 5

ExCA card status-changeregister (ExCA 804h/844h, see Section 5.5): bits 3−0

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ExCA card status-changeinterrupt configuration register (ExCA 805h/845h, see Section 5.6): bits 3−0

ExCA card detect and general control register (ExCA 816h/856h, see Section 5.19): bits 7, 6

Socket event register (CardBus offset 00h, see Section 6.1): bits 3−0

Socket mask register (CardBus offset 04h, see Section 6.2): bits 3−0

Socket present state register (CardBus offset 08h, see Section 6.3): bits 13−7, 5−1

Socket control register (CardBus offset 10h, see Section 6.5): bits 6−4, 2−0

Global reset-onlybits, as the name implies, are cleared only by GRST. These bits are never cleared by PRST, regardless of the setting of the PME enable bit. The GRST signal is gated only by the SUSPEND signal. This means that assertion of SUSPEND blocks the GRST signal internally, thus preserving all register contents. Figure 3−13 is a diagram showing the application of GRST and PRST.

The global reset-onlybits (functions 0 and 1) are:

Status register (PCI offset 06h, see Section 4.5): bits 15−11, 8

Secondary status register (PCI offset 16h, see Section 4.14): bits 15−11, 8

Subsystem vendor ID register (PCI offset 40h, see Section 4.26): bits 15–0

Subsystem ID register (PCI offset 42h, see Section 4.27): bits 15–0

PC Card 16-bitI/Flegacy-modebase-addressregister (PCI offset 44h, see Section 4.28): bits 31−0

System control register (PCI offset 80h, see Section 4.29): bits 31−24, 22−13, 11, 6−0

MC_CD debounce register (PCI offset 84h, see Section 4.30): bits 7−0

General control register (PCI offset 86h, see Section 4.31): bits 13−10, 7, 5−3, 1, 0

General-purposeevent status register (PCI offset 88h, see Section 4.32): bits 7, 6, 4−0

General-purposeevent enable register (PCI offset 89h, see Section 4.33): bits 7, 6, 4−0

General-purposeoutput register (PCI offset 8Bh, see Section 4.35): bits 4−0

Multifunction routing register (PCI offset 8Ch, see Section 4.36): bits 31−0

Retry status register (PCI offset 90h, see Section 4.37): bits 7−5, 3, 1

Card control register (PCI offset 91h, see Section 4.38): bits 7, 2−0

Device control register (PCI offset 92h, see Section 4.39): bits 7−5, 3−0

Diagnostic register (PCI offset 93h, see Section 4.40): bits 7−0

Power management capabilities register (PCI offset A2h, see Section 4.43): bit 15

Power management CSR register (PCI offset A4h, see Section 4.44): bits 15, 8

Serial bus data register (PCI offset B0h, see Section 4.47): bits 7−0

Serial bus index register (PCI offset B1h, see Section 4.48): bits 7−0

Serial bus slave address register (PCI offset B2h, see Section 4.49): bits 7−0

Serial bus control/status register (PCI offset B3h, see Section 4.50): bits 7, 3−0

ExCA identification and revision register (ExCA 800h/840h, see Section 5.1): bits 7−0

ExCA global control register (ExCA 81Eh/85Eh, see Section 5.20): bits 2−0

CardBus socket power management register (CardBus 20h, see Section 6.6): bits 25, 24

The global reset-onlybit (function 2) is:

Subsystem vendor ID register (PCI offset 2Ch, see Section 7.12): bits 15−0

Subsystem ID register (PCI offset 2Eh, see Section 7.12): bits 31−16

Minimum grant and maximum latency register (PCI offset 3Eh, see Section 7.16): bits 15−0

Power management control and status register (PCI offset 48h, see Section 7.20): bits 15, 8, 1, 0

Miscellaneous configuration register (PCI offset F0h, see Section 7.23): bits 15, 11−8, 5−0

Link enhancement control register (PCI offset F4h, see Section 7.24): bits 15−12, 10, 8, 7, 2, 1

Bus options register (OHCI offset 20h, see Section 8.9): bits 15−12

GUID high register (OHCI offset 24h, see Section 8.10): bits 31−0

GUID low register (OHCI offset 28h, see Section 8.11): bits 31−0

Host controller control register (OHCI offset 50h/54h, see Section 8.16): bit 23

Link control register (OHCI offset E0h/E4h, see Section 8.31): bit 6

PHY-linkloopback test register (Local offset C14h): bits 6−4, 0

Link test control register (Local offset C00h): bits 12−8

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The global reset-only(function 3) register bits:

Subsystem vendor ID register (PCI offset 2Ch, see Section 11.9): bits 15–0

Subsystem ID register (PCI offset 2Eh, see Section 11.10): bits 15–0

Power management control and status register (PCI offset 48h, see Section 11.18): bits 15, 8, 1, 0

General control register (PCI offset 4Ch, see Section 11.21): bits 6−4, 2–0

Diagnostic register (PCI offset 54h, see Section 11.23): bits 31–0

The global reset-only(function 4) register bits:

Subsystem vendor ID register (PCI offset 2Ch, see Section 12.9): bits 15–0

Subsystem ID register (PCI offset 2Eh, see Section 12.10): bits 15–0

Power management control and status register (PCI offset 84h, see Section 12.19): bits 15, 8, 1, 0

General control register (PCI offset 88h, see Section 12.22): bits 6−4, 0

Diagnostic register (PCI offset 90h, see Section 12.24): bits 31–0

The global reset-only(function 5) register bits:

Subsystem vendor ID register (PCI offset 2Ch, see Section 13.10): bits 15–0

Subsystem ID register (PCI offset 2Eh, see Section 13.11): bits 15–0

Power management control and status register (PCI offset 48h, see Section 13.19): bits 15, 8, 1, 0

General control register (PCI offset 4Ch, see Section 13.22): bits 6−4, 0

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3.9 IEEE 1394 Application Information

3.9.1PHY Port Cable Connection

PCI7x21/

 

400 k

PCI7x11

CPS

 

1 µF

TPBIAS

56

56

TPA+

TPA−

Cable Port

TPB+

TPB−

56

56

220 pF

5 k

(see Note A)

 

Cable

Power

Pair

Cable

Pair

A

Cable

Pair

B

Outer Shield

Termination

NOTE A: IEEE Std 1394-1995calls for a250-pFcapacitor, which is a nonstandard component value. A220-pFcapacitor is recommended.

Figure 3−17. TP Cable Connections

Outer Cable Shield

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 M

 

 

 

 

0.01 µF

 

 

 

 

0.001 µF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chassis Ground

Figure 3−18. Typical Compliant DC Isolated Outer Shield Termination

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Outer Cable Shield

Chassis Ground

Figure 3−19. Non-DCIsolated Outer Shield Termination

3.9.2Crystal Selection

The PCI7x21/PCI7x11 controller is designed to use an external 24.576-MHzcrystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates.

A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std1394-1995.Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHY devices must be able to compensate for this difference over the maximum packet length. Large clock variations may cause resynchronization overflows or underflows, resulting in corrupted packet data.

The following are some typical specifications for crystals used with the PHYs from TI in order to achieve the required frequency accuracy and stability:

Crystal mode of operation: Fundamental

Frequency tolerance @ 25°C: Total frequency variation for the complete circuit is±100 ppm. A crystal with

±30 ppm frequency tolerance is recommended for adequate margin.

Frequency stability (over temperature and age): A crystal with ±30 ppm frequency stability is recommended for adequate margin.

NOTE: The total frequency variation must be kept below±100 ppm from nominal with some allowance for error introduced by board and device variations.Trade-offsbetween frequency tolerance and stability may be made as long as the total frequency variation is less than

±100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone. Crystal aging also contributes to the frequency variation.

Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent

upon the load capacitance specified for the crystal. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also board layout and circuit. It is recommended that load capacitors with a maximum of±5% tolerance be used.

For example, load capacitors (C9 and C10 in Figure 3−20) of 16 pF each were appropriate for the layout of the PCI7x21/PCI7x11 evaluation module (EVM), which uses a crystal specified for 12-pFloading. The load specified for

the crystal includes the load capacitors (C9 and C10), the loading of the PHY pins (CPHY), and the loading of the board itself (CBD). The value of CPHY is typically about 1 pF, and CBD is typically 0.8 pF per centimeter of board etch; atypical board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors in series so that the

total load capacitance is:

CL+ C9C9 )C10C10 )CPHY)CBD

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C9

X1

 

 

 

 

X1

 

CPHY+ CBD

 

 

 

 

 

 

 

 

 

24.576 MHz

 

 

 

 

 

 

 

 

 

 

 

 

IS

 

 

X0

C10

Figure 3−20. Load Capacitance for the PCI7x21/PCI7x11 PHY

The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise introduced into the PHY phase-lockloop, and minimizing any emissions from the circuit. The crystal and two load capacitors must be considered as a unit during layout. The crystal and the load capacitors must be placed as close as possible to one another while minimizing the loop area created by the combination of the three components. Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the effect of the resonant current (Is) that flows in this resonant circuit. This layout unit (crystal and load capacitors) must then be placed as close as possible to the PHY X1 and X0 terminals to minimize etch lengths, as shown in Figure 3−21.

C9

 

C10

 

 

 

 

 

 

 

 

 

X1

For more details on crystal selection, see application report SLLA051 available from the TI website: http://www.ti.com/sc/1394.

Figure 3−21. Recommended Crystal and Capacitor Layout

3.9.3Bus Reset

In the PCI7x21/PCI7x11 controller, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization sequence. The IBR bit is located in PHY register 1, along with the root-holdoffbit (RHB) and Gap_Count field, as required by IEEE Std1394a-2000.Therefore, whenever the IBR bit is written, the RHB and Gap_Count are also written.

The RHB and Gap_Count may also be updated by PHY-configpackets. The PCI7x21/PCI7x11 controller is IEEE1394a-2000compliant, and therefore both the reception and transmission ofPHY-configpackets cause the RHB and Gap_Count to be loaded, unlike older IEEE1394-1995compliant PHY devices which decode only receivedPHY-configpackets.

The gap-countis set to the maximum value of 63 after 2 consecutive bus resets without an intervening write to the Gap_Count, either by a write to PHY register 1 or by aPHY-configpacket. This mechanism allows aPHY-configpacket to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have updated their RHBs and Gap_Count values, without having the Gap_Count set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which initiates a bus reset, then causes the Gap_Count of each node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, all other nodes on the bus have their Gap_Count values set to 63, while this node Gap_Count remains set to the value just loaded by the write to PHY register 1.

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Therefore, in order to maintain consistent gap-countsthroughout the bus, the following rules apply to the use of the IBR bit, RHB, and Gap_Count in PHY register 1:

Following the transmission of a PHY-configpacket, a bus reset must be initiated in order to verify that all nodes have correctly updated their RHBs and Gap_Count values and to ensure that a subsequent new connection to the bus causes the Gap_Count to be set to 63 on all nodes in the bus. If this bus reset is initiated by setting the IBR bit to 1, then the RHB and Gap_Count field must also be loaded with the correct values consistent with the just transmittedPHY-configpacket. In the PCI7x21/PCI7x11 controller, the RHB and Gap_Count are updated to their correct values upon the transmission of thePHY-configpacket, so these values may first be read from register 1 and then rewritten.

Other than to initiate the bus reset, which must follow the transmission of a PHY-configpacket, whenever the IBR bit is set to 1 in order to initiate a bus reset, the Gap_Count value must also be set to 63 so as to be consistent with other nodes on the bus, and the RHB must be maintained with its current value.

The PHY register 1 must not be written to except to set the IBR bit. The RHB and Gap_Count must not be written without also setting the IBR bit to 1.

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