Texas Instruments Dual-Single Socket CardBus and UntraMedia Controller PCI7621, Dual-Single Socket CardBus and UntraMedia Controller PCI7411, Dual-Single Socket CardBus and UntraMedia Controller PCI7421, Dual-Single Socket CardBus and UntraMedia Controller PCI7611 User Manual

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Table 2−5. PC Card Power Switch Terminals

Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power switch terminals.

TERMINAL

DESCRIPTION

I/O

INPUT

OUTPUT

EXTERNAL

NAME

NO.

TYPE

COMPONENTS

 

 

 

 

 

 

 

 

 

 

 

 

Power switch clock. Information on the DATA line is sampled at the rising edge of

 

 

 

PCMCIA power

CLOCK

L06

CLOCK. CLOCK defaults to an input, but can be changed to an output by using bit 27

I/O

TTLI1

TTLO1

switch

 

 

(P2CCLK) in the system control register (offset 80h, see Section 4.29).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

N01

Power switch data. DATA is used to communicate socket power control information

O

 

LVCO1

PCMCIA power

serially to the power switch.

 

switch

 

 

 

 

 

 

 

 

 

 

 

 

LATCH

N02

Power switch latch. LATCH is asserted by the controller to indicate to the power

O

 

LVCO1

PCMCIA power

switch that the data on the DATA line is valid.

 

switch

 

 

 

 

 

 

 

 

 

 

 

 

Table 2−6. PCI System Terminals

Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI terminals.

 

TERMINAL

 

 

DESCRIPTION

I/O

INPUT

POWER

EXTERNAL

 

NAME

NO.

 

 

TYPE

RAIL

COMPONENTS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Global reset. When the global reset is asserted, the

 

 

signal causes the

 

 

 

 

 

 

 

 

 

 

 

GRST

 

 

 

 

 

 

 

 

 

 

 

controller to place all output buffers in ahigh-impedancestate and reset all internal

 

 

 

 

 

 

 

 

 

 

 

registers. When GRST is asserted, the controller is completely in its default state. For

 

 

 

 

 

 

 

 

 

 

 

systems that requirewake-upfrom D3, GRST is normally asserted only during initial

 

 

 

Power-onreset or

 

GRST

T01

boot. PRST must be asserted following initial boot so that PME context is retained

I

LVCI2

 

 

 

 

 

 

 

 

tied to PRST

 

 

 

 

 

when transitioning from D3 to D0. For systems that do not requirewake-upfrom D3,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GRST must be tied to PRST. When the SUSPEND mode is enabled, the controller is

 

 

 

 

 

 

 

 

 

 

 

protected from the

GRST,

and the internal registers are preserved. All outputs are

 

 

 

 

 

 

 

 

 

 

 

placed in a high-impedancestate, but the contents of the registers are preserved.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCLK

P05

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI

I

PCII3

VCCP

 

 

 

 

signals are sampled at the rising edge of PCLK.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI bus reset. When the PCI bus reset is asserted,

 

 

causes the controller to

 

 

 

 

 

 

 

 

 

 

 

PRST

 

 

 

 

 

 

 

 

 

 

 

place all output buffers in ahigh-impedancestate and reset some internal registers.

 

 

 

 

 

 

 

 

 

 

 

When PRST is asserted, the controller is completely nonfunctional. After PRST is

 

 

 

 

 

 

 

PRST

 

R03

deasserted, the controller is in a default state.

I

PCII3

VCCP

 

 

 

 

 

 

 

 

When SUSPEND and PRST are asserted, the controller is protected from

PRST

 

 

 

 

 

 

 

 

 

 

 

 

clearing the internal registers. All outputs are placed in a high-impedancestate, but

 

 

 

 

 

 

 

 

 

 

 

the contents of the registers are preserved.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2−15

Table 2−7. PCI Address and Data Terminals

Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI address and data terminals.

TERMINAL

DESCRIPTION

I/O

INPUT

OUTPUT

POWER

NAME

NO.

TYPE

RAIL

 

 

 

 

 

 

 

 

 

 

 

 

AD31

U02

 

 

 

 

 

AD30

V01

 

 

 

 

 

AD29

V02

 

 

 

 

 

AD28

U03

 

 

 

 

 

AD27

W02

 

 

 

 

 

AD26

V03

 

 

 

 

 

AD25

U04

 

 

 

 

 

AD24

V04

 

 

 

 

 

AD23

V05

 

 

 

 

 

AD22

U05

 

 

 

 

 

AD21

R06

 

 

 

 

 

AD20

P06

 

 

 

 

 

AD19

W06

 

 

 

 

 

AD18

V06

 

 

 

 

 

AD17

U06

 

 

 

 

 

AD16

R07

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the

 

 

 

 

primary interface. During the address phase of a primary-busPCI cycle, AD31−AD0 contain a

I/O

PCII3

PCIO3

VCCP

AD15

V09

32-bitaddress or other destination information. During the data phase, AD31−AD0 contain data.

 

 

 

 

 

 

 

 

 

 

 

 

AD14

U09

 

 

 

 

 

AD13

R09

 

 

 

 

 

AD12

N09

 

 

 

 

 

AD11

V10

 

 

 

 

 

AD10

U10

 

 

 

 

 

AD9

R10

 

 

 

 

 

AD8

N10

 

 

 

 

 

AD7

V11

 

 

 

 

 

AD6

U11

 

 

 

 

 

AD5

R11

 

 

 

 

 

AD4

W12

 

 

 

 

 

AD3

V12

 

 

 

 

 

AD2

U12

 

 

 

 

 

AD1

N11

 

 

 

 

 

AD0

W13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W04

PCI-buscommands and byte enables. These signals are multiplexed on the same PCI

 

 

 

 

C/BE3

 

 

 

 

terminals. During the address phase of a primary-busPCI cycle, C/BE3−C/BE0 define the bus

 

 

 

 

 

 

 

W07

 

 

 

 

C/BE2

 

command. During the data phase, this 4-bitbus is used as byte enables. The byte enables

I/O

PCII3

PCIO3

VCCP

 

 

 

W09

determine which byte paths of the full32-bitdata bus carry meaningful data. C/BE0 applies to

C/BE1

 

 

 

W11

byte 0 (AD7−AD0), C/BE1 applies to byte 1 (AD15−AD8), C/BE2 applies to byte 2

 

 

 

 

C/BE0

 

 

 

 

(AD23−AD16), and C/BE3 applies to byte 3 (AD31−AD24).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI-busparity. In allPCI-busread and write cycles, the controller calculates even parity across

 

 

 

 

 

 

 

 

the AD31−AD0 and C/BE3 −C/BE0 buses. As an initiator during PCI cycles, the controller

 

 

 

 

PAR

P09

outputs this parity indicator with a one-PCLKdelay. As a target during PCI cycles, the controller

I/O

PCII3

PCIO3

VCCP

 

 

 

 

compares its calculated parity to the parity indicator of the initiator. A compare error results in

 

 

 

 

 

 

 

 

the assertion of a parity error (PERR).

 

 

 

 

 

 

 

 

 

 

 

 

 

2−16

Table 2−8. PCI Interface Control Terminals

Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI interface control terminals.

 

TERMINAL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DESCRIPTION

I/O

INPUT

OUTPUT

POWER

EXTERNAL

 

NAME

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TYPE

RAIL

COMPONENTS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI device select. The controller asserts

 

to claim a PCI cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

DEVSEL

 

 

 

 

 

 

 

 

 

 

 

 

N08

as the target device. As a PCI initiator on the bus, the controller monitors

I/O

PCII3

PCIO3

VCCP

Pullup resistor per

 

DEVSEL

 

DEVSEL until a target responds. If no target responds before timeout

PCI specification

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

occurs, then the controller terminates the cycle with an initiator abort.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI cycle frame.

 

 

 

 

 

 

 

 

 

 

 

 

is driven by the initiator of a bus cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FRAME

 

FRAME

 

 

 

 

 

 

 

 

 

 

 

 

 

V07

is asserted to indicate that a bus transaction is beginning, and data

I/O

PCII3

PCIO3

VCCP

Pullup resistor per

 

FRAME

 

transfers continue while this signal is asserted. When FRAME is

PCI specification

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

deasserted, the PCI bus transaction is in the final data phase.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI bus grant.

 

 

 

 

 

 

is driven by the PCI bus arbiter to grant the

 

 

 

 

 

 

 

 

 

 

 

 

 

GNT

 

 

 

 

 

 

 

 

 

 

 

 

T02

controller access to the PCI bus after the current data transaction has

I

PCII3

 

VCCP

 

 

GNT

 

 

 

completed. GNT may or may not follow a PCI bus request, depending on

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the PCI bus parking algorithm.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Initialization device select. IDSEL selects the controller during

 

 

 

 

 

 

IDSEL

W05

configuration space accesses. IDSEL can be connected to one of the

I

PCII3

 

VCCP

 

 

 

 

 

 

 

 

 

upper 24 PCI address lines on the PCI bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI initiator ready.

 

 

 

 

 

 

indicates the ability of the PCI bus initiator to

 

 

 

 

 

 

 

 

 

 

 

 

 

IRDY

 

 

 

 

 

 

 

 

 

 

 

 

 

complete the current data phase of the transaction. A dataphase is

 

 

 

 

Pullup resistor per

 

 

 

 

 

 

 

U07

completed on a rising edge of PCLK where both IRDY and TRDY are

I/O

PCII3

PCIO3

VCCP

 

IRDY

 

PCI specification

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

asserted. Until IRDY and TRDY are both sampled asserted, wait states

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

are inserted.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI parity error indicator.

 

 

is driven by a PCI controller to indicate

 

 

 

 

 

 

 

 

 

 

 

 

 

PERR

 

 

 

 

Pullup resistor per

 

PERR

V08

that calculated parity does not match PAR when PERR is enabled

I/O

PCII3

PCIO3

VCCP

 

PCI specification

 

 

 

 

 

 

 

 

through bit 6 of the command register (PCI offset 04h, see Section 4.4).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI bus request.

 

 

 

 

 

 

is asserted by the controller to request access to

 

 

 

 

 

 

 

 

 

 

 

 

U01

REQ

O

 

PCIO3

VCCP

 

 

REQ

 

 

 

the PCI bus as an initiator.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI system error.

 

 

 

 

 

 

is an output that is pulsed from the controller

 

 

 

 

 

 

 

 

 

 

 

 

 

SERR

 

 

 

 

 

 

 

 

 

 

 

 

 

when enabled through bit 8 of the command register (PCI offset 04h,

 

 

 

 

 

 

 

 

 

 

 

 

U08

see Section 4.4) indicating a system error has occurred. The controller

O

 

PCIO3

VCCP

Pullup resistor per

 

SERR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI specification

 

need not be the target of the PCI cycle to assert this signal. When SERR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is enabled in the command register, this signal also pulses, indicating

 

 

 

 

 

 

 

 

 

 

 

 

 

that an address parity error has occurred on a CardBus interface.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI cycle stop signal.

 

 

 

 

 

 

 

is driven by a PCI target to request the

 

 

 

 

 

 

 

 

 

 

 

 

 

STOP

 

 

 

 

 

 

 

 

 

 

 

 

W08

initiator to stop the current PCI bus transaction. STOP is used for target

I/O

PCII3

PCIO3

VCCP

Pullup resistor per

 

STOP

 

disconnects and is commonly asserted by target devices that do not

PCI specification

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

support burst data transfers.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI target ready.

 

 

 

 

 

 

indicates the ability of the primary bus target to

 

 

 

 

 

 

 

 

 

 

 

 

 

TRDY

 

 

 

 

 

 

 

 

 

 

 

 

 

complete the current data phase of the transaction. A dataphase is

 

 

 

 

Pullup resistor per

 

 

 

 

 

 

 

R08

completed on a rising edge ofPCLK when both IRDY and TRDY are

I/O

PCII3

PCIO3

VCCP

 

TRDY

 

PCI specification

 

 

 

 

 

 

 

 

asserted. Until both IRDY and TRDY are asserted, wait states are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

inserted.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2−17

Table 2−9. Multifunction and Miscellaneous Terminals

The power rail designation is not applicable for the multifunction and miscellaneous terminals.

 

TERMINAL

 

 

 

DESCRIPTION

I/O

INPUT

OUTPUT

PU/

EXTERNAL

PIN STRAPPING

 

NAME

 

NO.

 

 

TYPE

PD

COMPONENTS

(IF UNUSED)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E02

USB enable. These output terminals control an

 

 

 

 

 

 

A_USB_EN

 

 

 

 

 

 

 

 

external CBT switch for each socket when an USB

O

 

LVCO1

 

CBT switch

Float

B_USB_EN

 

E01

 

 

 

card is inserted into the socket.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_48

 

M01

A 48-MHzclock must be connected to this terminal.

I

LVCI1

 

 

48 MHz clock

 

 

 

 

source

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MFUNC0

 

N03

 

 

 

 

 

 

 

I/O

PCII3

PCIO3

 

 

10-kΩto47-kΩ

 

 

 

 

 

 

 

 

 

 

pullup resistor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MFUNC1

 

M05

 

 

 

 

 

 

 

I/O

PCII3

PCIO3

 

 

10-kΩto47-kΩ

 

 

 

 

 

 

 

 

 

 

pullup resistor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MFUNC2

 

P01

 

 

 

 

 

 

 

I/O

PCII3

PCIO3

 

 

10-kΩto47-kΩ

 

 

 

 

 

 

 

 

 

 

pullup resistor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Multifunction terminals 0−6. See Section 4.36,

 

 

 

 

 

 

MFUNC3

 

P02

I/O

PCII3

PCIO3

 

 

10-kΩto47-kΩ

 

Multifunction Routing Status Register, for

 

 

 

 

 

pullup resistor

 

 

 

 

 

 

 

configuration details.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MFUNC4

 

P03

I/O

PCII3

PCIO3

 

 

10-kΩto47-kΩ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pullup resistor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MFUNC5

 

N05

 

 

 

 

 

 

 

I/O

PCII3

PCIO3

 

 

10-kΩto47-kΩ

 

 

 

 

 

 

 

 

 

 

pullup resistor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MFUNC6

 

R01

 

 

 

 

 

 

 

I/O

PCII3

PCIO3

 

 

10-kΩto47-kΩ

 

 

 

 

 

 

 

 

 

 

pullup resistor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

W17

Reserved. This terminal has no connection

 

 

 

 

 

Float

 

anywhere within the package.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHY_TEST_

 

R17

PHY test pin. Not for customer use. It must be pulled

I

LVCI1

 

PD1

 

NA

MA

 

high with a 4.7-kΩresistor.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ring indicate out and power management event

 

 

 

 

 

 

RI_OUT/

 

 

 

 

 

 

Pullup resistor per

 

 

T03

output. This terminal provides an output for

O

 

LVCO2

 

NA

PME

 

 

 

PCI specification

 

 

ring-indicateor PME signals.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RSVD

 

T19

Reserved. This terminal has no connection

 

 

 

 

Float

 

anywhere within the package.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial clock. At

 

 

the SCL signal is sampled to

 

 

 

 

 

 

 

 

 

 

 

 

 

PRST,

 

 

 

 

 

 

 

 

 

 

 

 

 

determine if a two-wireserial ROM is present. If the

 

 

 

 

 

 

 

 

 

 

 

 

 

serial ROM is detected, then this terminal provides

 

 

 

 

Pullup resistor per

 

 

 

 

 

 

 

 

the serial clock signaling and is implemented as

 

 

 

 

I2C specification

Tie to GND if not

SCL

 

M03

open-drain.For normal operation (a ROM is

I/O

TTLI1

TTLO1

 

(value depends on

 

 

using EEPROM

 

 

 

 

 

 

 

implemented in the design), this terminal must be

 

 

 

 

EEPROM,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pulled high to the ROM VDD with a2.7-kΩresistor.

 

 

 

 

typically 2.7 kΩ)

 

 

 

 

 

 

 

 

Otherwise, it must be pulled low to ground with a

 

 

 

 

 

 

 

 

 

 

 

 

 

220-Ωresistor.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial data. This terminal is implemented as

 

 

 

 

Pullup resistor per

 

 

 

 

 

 

 

 

open-drain,and for normal operation (a ROM is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C specification

 

 

 

 

 

 

 

 

implemented in the design), this terminal must be

 

 

 

 

Tie to GND if not

SDA

 

M02

I/O

TTLI1

TTLO1

 

(value depends on

 

pulled high to the ROM VDD with a2.7-kΩresistor.

 

using EEPROM

 

 

 

 

 

 

 

 

 

 

 

EEPROM,

 

 

 

 

 

 

 

Otherwise, it must be pulled low to ground with a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

typically 2.7 kΩ)

 

 

 

 

 

 

 

 

220-Ωresistor.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Speaker output. SPKROUT is the output to the host

 

 

 

 

 

 

 

 

 

 

 

 

 

system that can carry SPKR or CAUDIO through the

 

 

 

 

10-kΩto47-kΩ

10-kΩto47-kΩ

SPKROUT

 

L07

controller from the PC Card interface. SPKROUT is

O

 

TTLO1

 

 

 

 

pulldown resistor

pulldown resistor

 

 

 

 

 

 

 

driven as theexclusive-ORcombination of card

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPKR//CAUDIO inputs.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Suspend.

 

 

protects the internal registers

 

 

 

 

 

 

 

 

 

 

 

 

 

SUSPEND

 

 

 

 

 

 

 

 

 

 

 

 

 

from clearing when the GRST or

PRST

signal is

 

 

 

 

10-kΩto47-kΩ

10-kΩto47-kΩ

SUSPEND

 

R02

I

PCII6

 

 

 

asserted. See Section 3.8.6, Suspend Mode, for

 

 

pullup resistor

pullup resistor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

details.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Terminal TEST0 is used for factory test of the

 

 

 

 

 

 

TEST0

 

P12

controller and must be connected to ground for

I/O

LVCI1

 

PD1

 

Tie to GND

 

 

 

 

 

 

 

normal operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2−18

Table 2−10. 16-BitPC Card Address and Data Terminals

External components are not applicable for the 16-bitPC Card address and data terminals. If any16-bitPC Card address and data terminal is unused, then the terminal may be left floating.

SOCKET A TERMINAL

SOCKET B TERMINAL

DESCRIPTION

I/O

POWER

NAME

NO.

NAME

NO.

TYPE

RAIL

 

 

 

 

 

 

 

 

A_A25

C07

B_A25

H14

 

 

 

A_A24

A07

B_A24

G17

 

 

 

A_A23

C08

B_A23

G19

 

 

 

A_A22

A08

B_A22

H17

 

 

 

A_A21

C09

B_A21

H19

 

 

 

A_A20

A09

B_A20

J17

 

 

 

A_A19

E10

B_A19

J19

 

 

 

A_A18

C10

B_A18

K15

 

 

 

A_A17

A10

B_A17

K17

 

 

 

A_A16

E09

B_A16

H18

 

 

 

A_A15

B08

B_A15

J13

 

 

 

A_A14

F10

B_A14

J18

 

 

 

A_A13

G10

B_A13

K13

PC Card address. 16-bitPC Card address lines. A25 is the most significant

O

VCCA/

A_A12

F09

B_A12

G18

bit.

VCCB

 

A_A11

B11

B_A11

L17

 

 

 

A_A10

A12

B_A10

M17

 

 

 

A_A9

G11

B_A9

K18

 

 

 

A_A8

B10

B_A8

K14

 

 

 

A_A7

B07

B_A7

H15

 

 

 

A_A6

G09

B_A6

F18

 

 

 

A_A5

B06

B_A5

G15

 

 

 

A_A4

C06

B_A4

E19

 

 

 

A_A3

B05

B_A3

E17

 

 

 

A_A2

E06

B_A2

D18

 

 

 

A_A1

A04

B_A1

C19

 

 

 

A_A0

B04

B_A0

D17

 

 

 

 

 

 

 

 

 

 

A_D15

E12

B_D15

M14

 

 

 

A_D14

B13

B_D14

N17

 

 

 

A_D13

F12

B_D13

N19

 

 

 

A_D12

C14

B_D12

N15

 

 

 

A_D11

A14

B_D11

P18

 

 

 

A_D10

D01

B_D10

B15

 

 

 

A_D9

C01

B_D9

A16

 

 

 

A_D8

C02

B_D8

A17

PC Card data. 16-bitPC Card data lines. D15 is the most significant bit.

I/O

VCCA/

A_D7

C13

B_D7

M15

VCCB

 

 

A_D6

A13

B_D6

N18

 

 

 

A_D5

E13

B_D5

M13

 

 

 

A_D4

B14

B_D4

P17

 

 

 

A_D3

E14

B_D3

P19

 

 

 

A_D2

D02

B_D2

A15

 

 

 

A_D1

D03

B_D1

B16

 

 

 

A_D0

B01

B_D0

C16

 

 

 

 

 

 

 

 

 

 

These terminals are reserved for the PCI7611 and PCI7411 controllers.

2−19

Table 2−11. 16-BitPC Card Interface Control Terminals

External components are not applicable for the 16-bitPC Card interface control terminals. If any16-bitPC Card interface control terminal is unused, then the terminal may be left floating.

 

SKT A TERMINAL

 

SKT B TERMINAL

 

 

 

 

 

 

 

 

 

 

 

 

 

DESCRIPTION

I/O

POWER

 

 

 

NAME

NO.

 

 

 

NAME

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

TYPE

RAIL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Battery voltage detect 1. BVD1 is generated by 16-bitmemory PC Cards that

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

include batteries. BVD1 is used with BVD2 as an indication of the condition of the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is good. When BVD2 is low and BVD1 is high, the battery is weak and must be

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

replaced. When BVD1 is low, the battery is no longer serviceable and the data in

 

 

 

 

A_BVD1

B02

 

 

B_BVD1

F14

the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt

I

VCCA/

 

 

 

 

Configuration Register, for enable bits. See Section 5.5,ExCA Card

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(STSCHG/RI)

(STSCHG/RI)

VCCB

 

 

Status-ChangeRegister, and Section 5.2, ExCA Interface Status Register, for the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

status bits for this signal.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Status change.

STSCHG

alerts the system to a change in the READY, write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

protect, or battery voltage dead condition of a 16-bitI/O PC Card.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ring indicate.

RI

is used by 16-bitmodem cards to indicate a ring detection.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Battery voltage detect 2. BVD2 is generated by 16-bitmemory PC Cards that

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

include batteries. BVD2 is used with BVD1 as an indication of the condition of the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is good. When BVD2 is low and BVD1 is high, the battery is weak and must be

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

replaced. When BVD1 is low, the battery is no longer serviceable and the data in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt

 

 

 

 

A_BVD2

 

 

 

B_BVD2

 

Configuration Register, for enable bits. See Section 5.5,ExCA Card

 

VCCA/

 

 

A02

 

 

C17

Status-ChangeRegister, and Section 5.2, ExCA Interface Status Register, for the

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCCB

 

 

(SPKR)

 

 

(SPKR)

status bits for this signal.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Speaker.

SPKR

 

is an optional binary audio signal available only when the card and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

socket have been configured for the 16-bitI/O interface. The audio signals from

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cards A and B are combined by the controller and are output on SPKROUT.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DMA request. BVD2 can be used as the DMA request signal during DMA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

operations to a 16-bitPC Card that supports DMA. The PC Card asserts BVD2 to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

indicate a request for a DMA operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Card detect 1 and card detect 2.

 

 

and

 

 

are internally connected to ground

 

 

 

 

 

 

 

 

 

 

C15

 

 

 

 

 

 

 

 

N13

CD1

CD2

 

 

 

 

 

A_CD1

 

 

 

B_CD1

 

 

 

 

 

 

 

 

on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are

I

 

 

 

 

A_CD2

E05

 

 

 

B_CD2

B17

 

 

 

 

 

 

 

pulled low. For signal status, see Section 5.2, ExCA Interface Status Register.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Card enable 1 and card enable 2.

 

 

and

 

 

enable evenand odd-numbered

 

 

 

 

 

 

 

 

 

 

G12

 

 

 

 

 

 

 

 

M18

CE1

CE2

 

VCCA/

 

 

 

A_CE1

 

 

 

B_CE1

 

 

 

 

 

 

 

address bytes. CE1 enables even-numberedaddress bytes, and CE2 enables

O

 

 

 

A_CE2

B12

 

 

 

B_CE2

L19

VCCB

 

 

 

 

 

 

odd-numberedaddress bytes.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input acknowledge.

 

 

is asserted by the PC Card when it can respond to an

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INPACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O read cycle at the current address.

 

VCCA/

 

A_INPACK

E07

 

B_INPACK

E18

DMA request. INPACK can be used as the DMA request signal during DMA

I

 

 

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

operations from a 16-bitPC Card that supports DMA. If it is used as a strobe, then

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the PC Card asserts this signal to indicate a request for a DMA operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O read.

 

 

 

 

is asserted by the controller to enable 16-bitI/O PC Card data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IORD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

output during host I/O read cycles.

 

VCCA/

 

 

A_IORD

C11

 

 

B_IORD

L15

DMA write. IORD is used as the DMA write strobe during DMA operations from a

O

 

 

 

 

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16-bitPC Card that supports DMA. The controller asserts IORD during DMA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

transfers from the PC Card to host memory.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O write.

 

 

 

 

 

is driven low by the controller to strobe write data into 16-bitI/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOWR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PC Cards during host I/O write cycles.

 

VCCA/

 

A_IOWR

E11

 

 

B_IOWR

L13

DMA read. IOWR is used as the DMA write strobe during DMA operations from a

O

 

 

 

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16-bitPC Card that supports DMA. The controller asserts IOWR during transfers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

from host memory to the PC Card.

 

 

These terminals are reserved for the PCI7611 and PCI7411 controllers.

2−20

Table 2−11. 16-BitPC Card Interface Control Terminals (Continued)

SKT A TERMINAL

SKT B TERMINAL

 

 

 

 

 

 

 

 

 

 

 

 

 

DESCRIPTION

I/O

POWER

 

 

 

NAME

NO.

 

 

 

NAME

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

TYPE

RAIL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output enable.

OE

is driven low by the controller to enable 16-bitmemory PC Card

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

data output during host memory read cycles.

 

VCCA/

 

 

 

A_OE

C12

 

 

 

 

B_OE

L18

DMA terminal count. OE is used as terminal count (TC) during DMA operations to a

O

 

 

 

 

 

 

 

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16-bitPC Card that supports DMA. The controller asserts OE to indicate TC for a DMA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ready. The ready function is provided when the 16-bitPC Card and the host socket are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

configured for the memory-onlyinterface. READY is driven low by16-bitmemory PC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cards to indicate that the memory card circuits are busy processing a previous write

 

 

A_READY

C04

B_READY

B19

command. READY is driven high when the 16-bitmemory PC Card is ready to accept a

I

VCCA/

 

 

(IREQ)

 

 

 

(IREQ)

new data transfer command.

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt request.

IREQ

is asserted by a 16-bitI/O PC Card to indicate to the host that a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

controller on the 16-bitI/O PC Card requires service by the host software. IREQ is high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(deasserted) when no interrupt is requested.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Attribute memory select.

REG

remains high for all common memory accesses. When

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

space

(IORD

or IOWR active). Attribute memory is a separately accessed section of

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

card memory and is generally used to record card capacity and other configuration and

 

VCCA/

 

 

A_REG

C05

 

B_REG

F15

attribute information.

O

 

 

 

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

operations to a 16-bitPC Card that supports DMA. The controller asserts REG to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR) or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DMA write (IORD) strobes to transfer data.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A_RESET

A06

B_RESET

F17

PC Card reset. RESET forces a hard reset to a 16-bitPC Card.

O

VCCA/

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A03

 

 

 

 

 

 

 

C18

Voltage sense 1 and voltage sense 2.

 

and

 

 

when used in conjunction with

 

VCCA/

 

 

 

A_VS1

 

 

 

 

 

B_VS1

 

 

VS1

VS2,

 

I/O

 

 

A_VS2

E08

 

 

 

B_VS2

F19

each other, determine the operating voltage of the PC Card.

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B03

 

 

 

 

 

 

 

B18

Bus cycle wait.

WAIT

is driven by a 16-bitPC Card to extend the completion of the

I

VCCA/

 

A_WAIT

B_WAIT

 

memory or I/O cycle in progress.

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write enable.

WE

is used to strobe memory write data into 16-bitmemory PC Cards.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE is also used for memory PC Cards that employ programmable memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

technologies.

 

 

 

VCCA/

 

 

 

A_WE

B09

 

 

 

B_WE

J15

O

 

 

 

 

 

 

DMA terminal count. WE is used as a TC during DMA operations to a16-bitPC Card

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

that supports DMA. The controller asserts WE to indicate the TC for a DMA read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write protect. WP applies to 16-bitmemory PC Cards. WP reflects the status of the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

write-protectswitch on 16-bitmemory PC Cards. For16-bitI/O cards, WP is used for

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the 16-bitport (IOIS16) function.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is asserted by the 16-bit

 

 

 

 

 

A_WP

 

 

 

 

 

B_WP

 

 

I/O is 16 bits.

IOIS16

applies to 16-bitI/O PC Cards.

IOIS16

 

VCCA/

 

 

 

C03

 

 

 

A18

PC Card when the address on the bus corresponds to an address to which the 16-bit

I

(IOIS16)

(IOIS16)

VCCB

 

 

PC Card responds, and the I/O port that is addressed is capable of 16-bitaccesses.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DMA request. WP can be used as the DMA request signal during DMA operations to a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16-bitPC Card that supports DMA. If used, then the PC Card asserts WP to indicate a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

request for a DMA operation.

 

 

These terminals are reserved for the PCI7611 and PCI7411 controllers.

2−21

Table 2−12. CardBus PC Card Interface System Terminals

A 33-Ωto47-Ωseries damping resistor (per PC Card specification) is the only external component needed for terminals B08 (A_CCLK) and H17 (B_CCLK). If any CardBus PC Card interface system terminal is unused, then the terminal may be left floating.

 

SKT A TERMINAL

 

SKT B TERMINAL

 

DESCRIPTION

I/O

INPUT

OUTPUT

PU/

POWER

 

NAME

NO.

 

NAME

NO.

 

TYPE

PD

RAIL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus clock. CCLK provides synchronous timing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

for all transactions on the CardBusinterface. All

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

signals except CRST, CCLKRUN, CINT, CSTSCHG,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CAUDIO, CCD2, CCD1, CVS2, and CVS1 are

 

 

 

 

VCCA/

 

A_CCLK

E09

B_CCLK

H18

sampled on the rising edge of CCLK, and all timing

O

 

PCIO3

 

 

 

 

VCCB

 

 

 

 

 

 

 

 

 

 

parameters are defined with the rising edge of this

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

signal. CCLK operates at the PCI bus clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

frequency, but it can be stopped in the low state or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

slowed down for power savings.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus clock run.

CCLKRUN

is used by a CardBus

 

 

 

 

 

 

 

 

 

C03

 

 

 

 

A18

PC Card to request an increase in the CCLK

I/O

PCII4

PCIO4

PU3

VCCA/

 

A_CCLKRUN

B_CCLKRUN

 

frequency, and by the controller to indicate that the

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CCLK frequency is going to be decreased.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus reset.

CRST

brings CardBus PC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Card-specificregisters, sequencers, and signals to a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

known state. When CRST is asserted, all CardBus

 

 

 

 

VCCA/

 

A_CRST

A06

B_CRST

F17

PC Card signals are placed in a high-impedance

O

PCII4

PCIO4

PU3

 

VCCB

 

 

 

 

 

 

 

 

 

 

state, and the controller drives these signals to a valid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

logic level. Assertion can be asynchronous to CCLK,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

but deassertion must be synchronous to CCLK.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

These terminals are reserved for the PCI7611 and PCI7411 controllers.

2−22

Table 2−13. CardBus PC Card Address and Data Terminals

External components are not applicable for the 16-bitPC Card address and data terminals. If any CardBus PC Card address and data terminal is unused, then the terminal may be left floating.

SKT A TERMINAL

SKT B TERMINAL

DESCRIPTION

I/O

INPUT

OUTPUT

POWER

NAME

NO.

NAME

NO.

TYPE

RAIL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A_CAD31

D01

B_CAD31

B15

 

 

 

 

 

 

 

 

 

 

A_CAD30

C01

B_CAD30

A16

 

 

 

 

 

 

 

 

 

 

A_CAD29

D03

B_CAD29

B16

 

 

 

 

 

 

 

 

 

 

A_CAD28

C02

B_CAD28

A17

 

 

 

 

 

 

 

 

 

 

A_CAD27

B01

B_CAD27

C16

 

 

 

 

 

 

 

 

 

 

A_CAD26

B04

B_CAD26

D17

 

 

 

 

 

 

 

 

 

 

A_CAD25

A04

B_CAD25

C19

 

 

 

 

 

 

 

 

 

 

A_CAD24

E06

B_CAD24

D18

 

 

 

 

 

 

 

 

 

 

A_CAD23

B05

B_CAD23

E17

 

 

 

 

 

 

 

 

 

 

A_CAD22

C06

B_CAD22

E19

 

 

 

 

 

 

 

 

 

 

A_CAD21

B06

B_CAD21

G15

 

 

 

 

 

 

 

 

 

 

A_CAD20

G09

B_CAD20

F18

 

 

 

 

 

 

 

 

 

 

A_CAD19

C07

B_CAD19

H14

 

 

 

 

 

 

 

 

 

 

A_CAD18

B07

B_CAD18

H15

 

 

 

 

 

 

 

 

 

 

A_CAD17

A07

B_CAD17

G17

CardBus address and data. These signals make up the multiplexed

 

 

 

 

A_CAD16

A10

B_CAD16

K17

CardBus address and data bus on the CardBus interface. During

 

 

 

VCCA/

the address phase of a CardBus cycle, CAD31−CAD0 contain a

I/O

PCII7

PCIO7

A_CAD15

E11

B_CAD15

L13

VCCB

32-bitaddress. During the data phase of a CardBus cycle,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A_CAD14

G11

B_CAD14

K18

CAD31−CAD0 contain data. CAD31 is the most significant bit.

 

 

 

 

A_CAD13

C11

B_CAD13

L15

 

 

 

 

 

 

 

 

 

 

A_CAD12

B11

B_CAD12

L17

 

 

 

 

 

 

 

 

 

 

A_CAD11

C12

B_CAD11

L18

 

 

 

 

 

 

 

 

 

 

A_CAD10

B12

B_CAD10

L19

 

 

 

 

 

 

 

 

 

 

A_CAD9

A12

B_CAD9

M17

 

 

 

 

 

 

 

 

 

 

A_CAD8

E12

B_CAD8

M14

 

 

 

 

 

 

 

 

 

 

A_CAD7

C13

B_CAD7

M15

 

 

 

 

 

 

 

 

 

 

A_CAD6

F12

B_CAD6

N19

 

 

 

 

 

 

 

 

 

 

A_CAD5

A13

B_CAD5

N18

 

 

 

 

 

 

 

 

 

 

A_CAD4

C14

B_CAD4

N15

 

 

 

 

 

 

 

 

 

 

A_CAD3

E13

B_CAD3

M13

 

 

 

 

 

 

 

 

 

 

A_CAD2

A14

B_CAD2

P18

 

 

 

 

 

 

 

 

 

 

A_CAD1

B14

B_CAD1

P17

 

 

 

 

 

 

 

 

 

 

A_CAD0

E14

B_CAD0

P19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus bus commands and byte enables.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CC/BE3−CC/BE0 are

 

 

 

 

 

 

 

 

 

 

 

 

multiplexed on the same CardBus terminals. During the address

 

 

 

 

 

 

 

C05

 

 

 

F15

 

 

 

 

 

 

 

 

 

 

A_CC/BE3

 

B_CC/BE3

phase of a CardBus cycle, CC/BE3−CC/BE0 define the bus

 

 

 

 

 

 

 

F09

 

 

 

G18

command. During the data phase, this 4-bitbus is used as byte

 

 

 

 

A_CC/BE2

B_CC/BE2

I/O

 

 

VCCA/

enables. The byte enables determine which byte paths of the full

PCII7

PCIO7

 

 

 

B10

 

 

 

K14

VCCB

A_CC/BE1

B_CC/BE1

 

 

 

 

 

 

 

 

 

32-bitdata bus carrymeaningful data. CC/BE0 applies to byte 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A_CC/BE0

 

G12

B_CC/BE0

M18

(CAD7−CAD0), CC/BE1 applies to byte 1 (CAD15−CAD8),

 

 

 

 

 

 

 

 

 

 

 

 

CC/BE2 applies to byte 2 (CAD23−CAD16), and CC/BE3 applies to

 

 

 

 

 

 

 

 

 

 

 

 

byte 3 (CAD31−CAD24).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus parity. In all CardBus read and write cycles, the controller

 

 

 

 

 

 

 

 

 

 

 

 

calculates even parity across the CAD and CC/BE buses. As an

 

 

 

 

A_CPAR

G10

B_CPAR

K13

initiator during CardBus cycles, the controller outputs CPAR with a

I/O

PCII7

PCIO7

VCCA/

one-CCLKdelay. As a target during CardBus cycles, the controller

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

compares its calculated parity to the parity indicator of the initiator;

 

 

 

 

 

 

 

 

 

 

 

 

a compare error results in a parity error assertion.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

These terminals are reserved for the PCI7611 and PCI7411 controllers.

2−23

Table 2−14. CardBus PC Card Interface Control Terminals

If any CardBus PC Card interface control terminal is unused, then the terminal may be left floating.

 

 

 

SKT A TERMINAL

 

 

SKT B TERMINAL

 

 

 

DESCRIPTION

I/O

INPUT

OUTPUT

PU/

POWER

 

 

 

 

 

 

NAME

NO.

 

 

 

 

 

 

NAME

NO.

 

 

 

TYPE

PD

RAIL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus audio. CAUDIO is a digital input signal from

 

 

 

 

 

 

 

A_CAUDIO

A02

 

 

B_CAUDIO

C17

a PC Card to the system speaker. The controller

I

PCII4

PCIO4

PU3

VCCA/

 

 

 

 

supports the binary audio mode and outputs a binary

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

signal from the card to SPKROUT.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCCA/

 

 

 

 

 

 

 

 

 

 

 

 

 

E10

 

 

 

 

 

 

 

 

 

 

 

 

 

J19

CardBus lock.

CBLOCK

 

 

is used to gain exclusive

I/O

PCII4

PCIO4

PU3

 

 

A_CBLOCK

 

 

B_CBLOCK

 

 

 

 

access to a target.

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus detect 1 and CardBus detect 2.

CCD1

and

 

 

 

 

 

 

 

 

 

 

A_CCD1

 

 

 

 

 

C15

 

 

 

 

 

B_CCD1

 

 

 

 

 

N13

CCD2 are used in conjunction with CVS1 and CVS2

I

TTLI2

 

PU4

 

 

 

 

 

A_CCD2

E05

 

 

 

 

 

B_CCD2

B17

to identify card insertion and interrogate cards to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

determine the operating voltage and card type.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus device select. The controller asserts

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CDEVSEL to claim a CardBus cycle as the target

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C09

 

 

 

 

 

 

 

 

 

 

 

 

 

H19

device. As a CardBus initiator on the bus, the

I/O

PCII4

PCIO4

PU3

VCCA/

A_CDEVSEL

 

B_CDEVSEL

 

controller monitors CDEVSEL until a target responds.

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

If no target responds before timeout occurs, then the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

controller terminates the cycle with an initiator abort.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus cycle frame.

CFRAME

is driven by the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

initiator of a CardBus bus cycle. CFRAME is asserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C08

 

 

 

 

 

 

 

 

 

 

 

 

 

G19

to indicate that a bus transaction is beginning, and

I/O

PCII7

PCIO7

 

VCCA/

 

 

A_CFRAME

 

B_CFRAME

 

 

 

 

data transfers continue while this signal is asserted.

 

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When CFRAME is deasserted, the CardBus bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

transaction is in the final data phase.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus bus grant.

CGNT

is driven by the controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B09

 

 

 

 

 

 

 

 

 

 

 

 

 

J15

to grant a CardBus PC Card access to the CardBus

O

PCII7

PCIO7

 

VCCA/

 

 

 

 

A_CGNT

 

 

 

 

B_CGNT

 

 

 

 

 

 

 

 

 

bus after the current data transaction has been

 

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

completed.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCCA/

 

 

 

 

 

 

 

 

 

 

 

 

 

C04

 

 

 

 

 

 

 

 

 

 

 

 

 

B19

CardBus interrupt.

CINT

 

is asserted low by a CardBus

I

PCII4

PCIO4

PU3

 

 

 

 

 

A_CINT

 

 

 

 

 

 

B_CINT

 

 

 

 

 

 

 

 

 

 

 

PC Card to request interrupt servicing from the host.

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus initiator ready.

CIRDY

indicates the ability of

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the CardBus initiator to complete the current data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B08

 

 

 

 

 

 

 

 

 

 

 

 

 

J13

phase of the transaction. A data phase is completed

I/O

PCII4

PCIO4

PU3

VCCA/

 

 

 

 

A_CIRDY

 

 

 

 

B_CIRDY

 

 

 

 

 

 

 

 

on a rising edge of CCLK when both CIRDY and

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CTRDY are asserted. Until CIRDY and CTRDY are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

both sampled asserted, wait states are inserted.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus parity error.

CPERR

reports parity errors

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

F10

 

 

 

 

 

 

 

 

 

 

 

 

 

J18

during CardBus transactions, except during special

I/O

PCII4

PCIO4

PU3

VCCA/

 

 

 

A_CPERR

 

 

 

B_CPERR

 

 

 

 

 

 

cycles. It is driven low by a target two clocks following

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the data cycle during which a parity error is detected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus request.

CREQ

indicates to the arbiter that

 

 

 

 

VCCA/

 

 

 

 

A_CREQ

E07

 

 

 

 

B_CREQ

E18

the CardBus PC Card desires use of the CardBus bus

I

PCII4

PCIO4

PU3

 

 

 

 

 

 

 

 

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

as an initiator.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus system error.

CSERR

reports address parity

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

errors and other system errors that could lead to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

catastrophic results. CSERR is driven by the card

 

 

 

 

VCCA/

 

 

 

A_CSERR

B03

 

 

 

B_CSERR

B18

synchronous to CCLK, but deasserted by a weak

I

PCII4

PCIO4

PU3

 

 

 

 

 

 

VCCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pullup; deassertion may take several CCLK periods.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The controller can report CSERR to the system by

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

assertion of SERR on the PCI interface.

 

 

 

 

 

These terminals are reserved for the PCI7611 and PCI7411 controllers.

2−24