Texas Instruments Dual-Single Socket CardBus and UntraMedia Controller PCI7621 User Manual

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14 Electrical Characteristics

14.1 Absolute Maximum Ratings Over Operating Temperature Ranges

Supply voltage range, VR_PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . −0.2 V to 2.2 V

AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . −0.3 V to 4 V

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . −0.3 V to 4 V

VDPLL_15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . −0.5 V to 1.836 V

VDPLL_33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . −0.3 V to 4 V

VCCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . −0.5 V to 5.5

V

VCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . −0.5 V to 5.5

V

VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . −0.5 V to 5.5

V

SC_VCC_5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . −0.5 V to 5.5 V

Clamping voltage range, VCCP, VCCA, and VCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . −0.5 V to 6

V

Input voltage range, VI: PCI, CardBus, PHY, SC, miscellaneous . . . . . . . . . . . . . . . . . . .

−0.5 V to V CC + 0.5 V

Output voltage range, VO: PCI, CardBus, PHY, SC, miscellaneous . . . . . . . . . . . . . . . .

−0.5 V to V CC + 0.5 V

Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . ±20 mA

Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . ±20 mA

Human Body Model (HBM) ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . 1500 V

Operating free-airtemperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . 0°C to 70°C

Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . −65 °C to 150°C

Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . 150°C

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure toabsolute-maximum-ratedconditions for extended periods may affect device reliability.

NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply tofail-safeterminals. PCI terminals and miscellaneous terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to CardBus VCC. The limit specified applies for a dc condition.

2.Applies for external output and bidirectional buffers. VO > VCC does not apply tofail-safeterminals. PCI terminals and miscellaneous terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to CardBus VCC. The limit specified applies for a dc condition.

14.2Recommended Operating Conditions (see Note 3)

 

 

OPERATION

MIN

NOM

MAX

UNIT

 

 

 

 

 

 

 

VR_PORT

(see Table 2−4 for description)

1.8 V

1.6

1.8

2

V

 

 

 

 

 

 

 

AVDD

 

3.3 V

3

3.3

3.6

V

VCC

 

3.3 V

3

3.3

3.6

V

VDPLL_15

 

1.5 V

1.35

1.5

1.65

V

 

 

 

 

 

 

 

VDPLL_33

 

3.3 V

3

3.3

3.6

V

 

 

 

 

 

 

 

VCCP

PCI and miscellaneous I/O clamp voltage

3.3 V

3

3.3

3.6

V

 

 

 

 

5 V

4.75

5

5.25

 

 

 

 

 

 

 

 

 

 

VCCA

PC Card I/O clamp voltage

3.3 V

3

3.3

3.6

V

 

 

 

 

5 V

4.75

5

5.25

 

 

 

 

 

 

 

 

 

 

VCCB

PC Card I/O clamp voltage

3.3 V

3

3.3

3.6

V

 

 

 

 

5 V

4.75

5

5.25

 

 

 

 

 

 

 

 

 

 

SC_VCC_5V

 

5 V

4.75

5

5.25

V

 

 

 

 

 

 

NOTE 3: Unused terminals (input or I/O) must be held high or low to prevent them from floating.

 

 

 

 

14−1

Recommended Operating Conditions (continued)

 

 

 

 

 

 

OPERATION

MIN

NOM

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCIk

 

3.3 V

0.5 VCCP

 

VCCP

 

 

 

 

 

5 V

2

 

VCCP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.3 V CardBus

0.475 VCC(A/B)

 

VCC(A/B)

 

VIH

High-levelinput

 

PC Card

 

3.3 V 16-bit

2

 

VCC(A/B)

V

voltage

 

 

 

 

5 V 16-bit

2.4

 

VCC(A/B)

 

 

 

 

 

 

 

 

 

 

PC(0−2)

 

0.7 VCC

 

VCC

 

 

 

 

Miscellaneous

 

2

 

VCC

 

 

 

 

SC_DATA, SC_FCB, SC_RFU

 

0.6 SC_VCC_5V

 

SC_VCC_5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCIk

 

3.3 V

0

 

0.3 VCCP

 

 

 

 

 

5 V

0

 

0.8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.3 V CardBus

0

 

0.325 VCC(A/B)

 

V

Low-levelinput

 

PC Card

 

3.3 V 16-bit

0

 

0.8

V

 

 

 

 

 

 

 

 

 

IL

voltage

 

 

 

 

5 V 16-bit

0

 

0.8

 

 

 

 

 

 

 

 

 

 

 

PC(0−2)

 

0

 

0.2 VCC

 

 

 

 

Miscellaneous

 

0

 

0.8

 

 

 

 

SC_DATA, SC_FCB, SC_RFU

 

0

 

0.5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCIk

 

0

 

VCCP

 

VI

Input voltage

 

PC Card

 

0

 

VCC(A/B)

V

 

Miscellaneous

 

0

 

VCC

 

 

 

 

 

 

 

 

 

SC_DATA, SC_FCB, SC_RFU

 

0

 

SC_VCC_5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCIk

 

0

 

VCC

 

V §

Output voltage

 

PC Card

 

0

 

VCC

V

 

 

 

 

 

 

 

 

O

 

 

Miscellaneous

 

0

 

VCC

 

 

 

 

 

 

 

 

 

 

SC_CLK, SC_DATA, SC_FCB, SC_RFU, SC_RST

0

 

SC_VCC_5V

 

 

 

 

 

 

 

 

 

 

 

 

Input transition time

 

PCI and PC Card

 

1

 

4

 

 

 

 

 

 

 

 

 

 

 

t

 

Miscellaneous

 

0

 

6

ns

 

 

 

 

t

(tr and tf)

 

 

 

 

 

 

 

 

 

 

SC_DATA, SC_FCB, SC_RFU

 

0

 

1200

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IO

Output current

 

TPBIAS outputs

 

−5.6

 

1.3

mA

VID

Differential input

 

Cable inputs during data reception

118

 

260

mV

voltage

 

Cable inputs during arbitration

 

168

 

265

VIC

Common-mode

 

TPB cable inputs, source power node

0.4706

 

2.515

V

input voltage

 

TPB cable inputs, nonsource power node

0.4706

 

2.015

tPU

Powerup reset time

 

 

input

 

2

 

 

ms

 

GRST

 

 

 

Applies to external inputs and bidirectional buffers without hysteresis

Miscellaneous terminals are A03, B17, C15, C18, E05, E08, F19, H03,J01, J02,J03, J05, J06, J07,L02, L03, L05, M01, M02, M03, N01, N02, N13, P12, P15, R02, R17, T01 (A_CCDx, A_CDx, A_CVSx, A_VSx, B_CCDx, B_CDx, B_CVSx, B_VSx, SD_DAT0, SD_DAT2, SD_DAT3, SD_CMD, SD_CLK, SD_DAT1, SM_CLE, SC_CD, SC_OC, SC_PWR_CTRL, CLK_48, SDA, SCL, DATA, LATCH, TEST0, CNA, SUSPEND,

PHY_TEST_MA, and GRST terminals). § Applies to external output buffers

For a node that does not source power, see Section 4.2.2.2 in IEEE Std 1394a−2000.

# These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.kMFUNC(0:6) share the same specifications as the PCI terminals.

14−2

Recommended Operating Conditions (continued)

 

 

 

OPERATION

MIN

NOM

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

S100 operation

 

 

±1.08

 

 

 

 

 

 

 

 

 

 

Receive input jitter

TPA, TPB cable inputs

S200 operation

 

 

±0.5

ns

 

 

 

S400 operation

 

 

±0.315

 

 

 

 

 

 

 

 

 

 

 

 

S100 operation

 

 

±0.8

 

 

 

 

 

 

 

 

 

 

Receive input skew

Between TPA and TPB cable inputs

S200 operation

 

 

±0.55

ns

 

 

 

S400 operation

 

 

±0.5

 

 

 

 

 

 

 

 

 

TA

Operating ambient temperature range

 

0

25

70

°C

TJ#

Virtual junction temperature

 

 

0

25

115

°C

Applies to external inputs and bidirectional buffers without hysteresis

Miscellaneous terminals are A03, B17, C15, C18, E05, E08, F19, H03,J01, J02,J03, J05, J06, J07,L02, L03, L05, M01, M02, M03, N01, N02, N13, P12, P15, R02, R17, T01 (A_CCDx, A_CDx, A_CVSx, A_VSx, B_CCDx, B_CDx, B_CVSx, B_VSx, SD_DAT0, SD_DAT2, SD_DAT3,

SD_CMD, SD_CLK, SD_DAT1, SM_CLE, SC_CD, SC_OC, SC_PWR_CTRL, CLK_48, SDA, SCL, DATA, LATCH, TEST0, CNA, SUSPEND, PHY_TEST_MA, and GRST terminals).

§ Applies to external output buffers

For a node that does not source power, see Section 4.2.2.2 in IEEE Std 1394a−2000.

# These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.kMFUNC(0:6) share the same specifications as the PCI terminals.

14−3

14.3Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted)

 

PARAMETER

TERMINALS

OPERATION

TEST CONDITIONS

MIN

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

PCI

3.3 V

IOH = −0.5 mA

0.9 VCC

 

 

 

 

5 V

IOH = −2 mA

2.4

 

 

 

 

 

 

 

VOH

High-leveloutput voltage

 

3.3 V CardBus

IOH = −0.15 mA

0.9 VCC

 

V

PC Card

3.3 V 16-bit

IOH = −0.15 mA

2.4

 

 

 

 

 

 

 

 

5 V 16-bit

IOH = −0.15 mA

2.8

 

 

 

 

Miscellaneous§

 

I

OH

= −4 mA

V −0. 6

 

 

 

 

 

 

 

 

CC

 

 

 

 

PCI

3.3 V

IOL = 1.5 mA

 

0.1 VCC

 

 

 

5 V

IOL = 6 mA

 

0.55

 

 

 

 

 

 

VOL

Low-leveloutput voltage

 

3.3 V CardBus

IOL = 0.7 mA

 

0.1 VCC

V

PC Card

3.3 V 16-bit

IOL = 0.7 mA

0.4

 

 

 

 

 

 

 

 

5 V 16-bit

IOL = 0.7 mA

 

0.55

 

 

 

Miscellaneous§

 

I

OL

= 4 mA

 

0.5

 

 

 

 

 

 

 

 

 

 

IOZ

3-stateoutputhigh-impedance

Output terminals

3.6 V

VO = VCC or GND

 

±20

A

IOZL

High-impedance,low-level

Output terminals

3.6 V

VI = VCC

 

−1

A

output current

5.25 V

VI = VCC

 

−1

 

 

 

 

IOZH

High-impedance,high-level

Output terminals

3.6 V

VI = VCC

 

10

A

output current

5.25 V

VI = VCC

 

25

 

 

 

 

IIL

Low-levelinput current

Input terminals

3.6 V

VI = GND

 

±20

A

I/O terminals

3.6 V

VI = GND

±20

 

 

 

 

 

 

 

PCI

3.6 V

VI = VCC

 

±20

 

 

 

Others

3.6 V

VI = VCC

±20

 

 

IIH

High-levelinput current

Input terminals

3.6 V

VI = VCC

 

10

A

5.25 V

VI = VCC

 

20

 

 

 

 

 

 

 

I/O terminals

3.6 V

VI = VCC

 

10

 

 

 

5.25 V

VI = VCC

 

25

 

 

 

 

 

 

For PCI and miscellaneous terminals, VI = VCCP. For PC Card terminals, VI = VCC(A/B).

For I/O terminals, input leakage (IIL and IIH) includes IOZ leakage of the disabled output.

§Miscellaneous terminals are A03, B17, C15, C18, E05, E08, F19, H03,J01, J02,J03, J05, J06, J07,L02, L03, L05, M01, M02, M03, N01, N02, N13, P12, P15, R02, R17, T01 (A_CCDx, A_CDx, A_CVSx, A_VSx, B_CCDx, B_CDx, B_CVSx, B_VSx, SD_DAT0, SD_DAT2, SD_DAT3, SD_CMD, SD_CLK, SD_DAT1, SM_CLE, SC_CD, SC_OC, SC_PWR_CTRL, CLK_48, SDA, SCL, DATA, LATCH, TEST0, CNA, SUSPEND,

PHY_TEST_MA, and GRST terminals).

14−4

14.4Electrical Characteristics Over Recommended Ranges of Operating Conditions (unless otherwise noted)

14.4.1

Device

 

 

 

 

 

 

 

 

 

 

 

PARAMETER

TEST CONDITION

MIN

MAX

UNIT

 

 

 

 

 

 

VTH

Power status threshold, CPS input

400-kΩresistor

4.7

7.5

V

VO

TPBIAS output voltage

At rated IO current

1.665

2.015

V

II

Input current (PC0−PC2 inputs)

VCC = 3.6 V

 

5

µA

Measured at cable power side of resistor.

14.4.2

Driver

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PARAMETER

 

 

 

 

TEST CONDITION

 

 

MIN

MAX

 

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOD

Differential output voltage

 

56 Ω, See Figure 14−1

 

 

172

265

 

mV

IDIFF

Driver difference current, TPA+, TPA−, TPB+, TPB−

 

Drivers enabled, speed signaling off

 

−1.05

1.05

 

mA

I

Common-modespeed signaling current, TPB+, TPB−

 

S200 speed signaling enabled

 

−4.84

−2.53

 

mA

SP200

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

Common-modespeed signaling current, TPB+, TPB−

 

S400 speed signaling enabled

 

−12.4

−8.10

 

mA

SP400

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOFF

Off state differential voltage

 

Drivers disabled, See Figure 14−1

 

 

 

20

 

mV

Limits defined as algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− algebraic sum of driver cu

rrents.

Limits defined as absolute limit of each of TPB+ and TPB− driver currents.

 

 

 

 

 

 

 

 

 

TPAx+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TPBx+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

56

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TPAx−

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TPBx−

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 14−1. Test Load Diagram

 

 

 

 

 

 

 

14.4.3

Receiver

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PARAMETER

 

 

 

TEST CONDITION

 

MIN

TYP

MAX

 

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZID

 

Differential impedance

Drivers disabled

 

4

7

 

 

kΩ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZIC

 

Common-modeimpedance

Drivers disabled

 

20

 

 

 

kΩ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

24

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VTH−R

 

Receiver input threshold voltage

Drivers disabled

 

−30

 

30

 

mV

 

VTH−CB

 

Cable bias detect threshold, TPBx cable inputs

Drivers disabled

 

0.6

 

1.0

 

V

 

VTH+

 

Positive arbitration comparator threshold voltage

Drivers disabled

 

89

 

168

 

mV

 

VTH

 

Negative arbitration comparator threshold voltage

Drivers disabled

 

−168

 

−89

 

mV

 

VTH−SP200

Speed signal threshold

TPBIAS−TPA common mode

 

49

 

131

 

mV

 

VTH−SP400

Speed signal threshold

voltage, drivers disabled

 

314

 

396

 

mV

 

 

 

 

 

 

 

 

 

 

14−5

14.5PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-AirTemperature

 

PARAMETER

ALTERNATE

TEST CONDITIONS

MIN

MAX

UNIT

 

SYMBOL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tc

Cycle time, PCLK

tcyc

 

30

 

ns

tw(H)

Pulse duration (width), PCLK high

thigh

 

11

 

ns

tw(L)

Pulse duration (width), PCLK low

tlow

 

11

 

ns

tr, tf

Slew rate, PCLK

v/t

 

1

4

V/ns

tw

Pulse duration (width),

 

 

trst

 

1

 

ms

GRST

 

 

 

tsu

Setup time, PCLK active at end of PRST

trst-clk

 

100

 

ms

14.6 Switching Characteristics for PHY Port Interface

 

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

 

 

 

 

 

 

 

Jitter, transmit

Between TPA and TPB

 

± 0.15

ns

 

 

 

 

 

 

 

Skew, transmit

Between TPA and TPB

 

± 0.10

ns

 

 

 

 

 

 

tr

TP differential rise time, transmit

10% to 90%, at 1394 connector

0.5

1.2

ns

tf

TP differential fall time, transmit

90% to 10%, at 1394 connector

0.5

1.2

ns

14.7 Operating, Timing, and Switching Characteristics of XI

 

PARAMETER

MIN

TYP

MAX

UNIT

 

 

 

 

 

 

VDD

 

3.0

3.3

3.6

V (PLLVCC)

VIH

High-levelinput voltage

 

0.63VCC

 

V

VIL

Low-levelinput voltage

 

 

0.33VCC

V

 

Input clock frequency

 

24.576

 

MHz

 

 

 

 

 

 

 

Input clock frequency tolerance

 

 

<100

PPM

 

 

 

 

 

 

 

Input slew rate

0.2

 

4

V/ns

 

 

 

 

 

 

 

Input clock duty cycle

40%

 

60%

 

 

 

 

 

 

 

14.8PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-AirTemperature

This data manual uses the following conventions to describe time ( t ) intervals. The format is tA, wheresubscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td (ten, tdis) = delay time, tsu = setup time, and th = hold time.

 

PARAMETER

ALTERNATE

TEST CONDITIONS

MIN MAX

UNIT

 

 

SYMBOL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCLK-to-sharedsignal

 

 

tval

 

 

 

11

 

 

 

 

valid delay time

 

 

CL = 50 pF,

 

tpd

Propagation delay time, See Note 4

 

 

 

 

 

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCLK-to-sharedsignal

 

 

tinv

See Note 4

2

 

 

 

invalid delay time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ten

Enable time, high impedance-to-activedelay time from PCLK

 

 

ton

 

 

 

2

ns

tdis

Disable time, active-to-highimpedance delay time from PCLK

 

 

toff

 

 

 

28

ns

tsu

Setup time before PCLK valid

 

 

tsu

 

 

 

7

ns

th

Hold time after PCLK high

 

 

th

 

 

 

0

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE 4: PCI shared signals are AD31−AD0, C/BE3 −C/BE0 , FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.

14−6

15 Mechanical Information

The PCI7x21/PCI7x11 device is available in the 288-terminalMicroStar BGA package (GHK) or the288-terminallead (Pb atomic number 82) free MicroStar BGA package (ZHK). The following figure shows the mechanical dimensions for the GHK package. The GHK and ZHK packages are mechanically identical; therefore, only the GHK mechanical drawing is shown.

GHK (S-PBGA-N288)

PLASTIC BALL GRID ARRAY

16,10

 

 

 

 

14,40 TYP

 

 

 

 

15,90 SQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0,80

 

 

 

 

 

 

 

W

 

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

U

 

 

 

 

 

 

 

 

 

 

 

T

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

N

 

 

 

 

 

 

 

 

 

0,80

 

M

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

J

 

 

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

 

 

 

F

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

D

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

 

 

B

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

A1 Corner

1

3

5

7

9

11

13

15

17

19

 

 

2

4

6

8

10

12

 

14

16

18

0,95

 

 

 

 

Bottom View

 

 

 

0,85

1,40 MAX

 

 

 

 

 

 

 

 

 

 

 

 

Seating Plane

 

 

 

 

 

 

 

0,55

 

0,12

 

 

 

 

 

 

 

 

0,08

0,45

 

 

 

 

 

 

 

 

0,45

0,35

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4145273-4/E08/02

NOTES: B. All linear dimensions are in millimeters.

C.This drawing is subject to change without notice.

D.MicroStar BGA configuration.

MicroStar BGA is a trademark of Texas Instruments.

15−1

15−2

PACKAGE OPTION ADDENDUM

www.ti.com

18-Oct-2005

 

 

PACKAGING INFORMATION

Orderable Device

Status (1)

Package

Package

Pins Package Eco Plan (2)

Lead/Ball Finish

MSL Peak Temp (3)

 

 

Type

Drawing

 

Qty

 

 

 

PCI7411GHK

ACTIVE

BGA

GHK

288

1

TBD

Call TI

Level-3-220C-168HR

PCI7411ZHK

ACTIVE

BGA MI

ZHK

288

1

Green (RoHS &

Call TI

Level-3-260C-168HRS

 

 

CROSTA

 

 

 

no Sb/Br)

 

 

 

 

R

 

 

 

 

 

 

PCI7421GHK

ACTIVE

BGA

GHK

288

90

TBD

Call TI

Level-3-220C-168HR

PCI7421ZHK

ACTIVE

BGA MI

ZHK

288

90

Green (RoHS &

Call TI

Level-3-260C-168HRS

 

 

CROSTA

 

 

 

no Sb/Br)

 

 

 

 

R

 

 

 

 

 

 

PCI7611GHK

ACTIVE

BGA

GHK

288

90

TBD

Call TI

Level-3-220C-168HR

PCI7611ZHK

ACTIVE

BGA MI

ZHK

288

90

Green (RoHS &

Call TI

Level-3-260C-168HRS

 

 

CROSTA

 

 

 

no Sb/Br)

 

 

 

 

R

 

 

 

 

 

 

PCI7621GHK

ACTIVE

BGA

GHK

288

90

TBD

Call TI

Level-3-220C-168HR

PCI7621ZHK

ACTIVE

BGA MI

ZHK

288

90

Green (RoHS &

Call TI

Level-3-260C-168HRS

 

 

CROSTA

 

 

 

no Sb/Br)

 

 

 

 

R

 

 

 

 

 

 

(1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and alifetime-buyperiod is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2)Eco Plan - The planned eco-friendlyclassification:Pb-Free(RoHS) or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: ThePb-Free/Greenconversion plan has not been defined.

Pb-Free (RoHS): TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TIPb-Freeproducts are suitable for use in specifiedlead-freeprocesses.

Green (RoHS & no Sb/Br): TI defines "Green" to meanPb-Free(RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)MSL, Peak Temp. --The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page1