Texas Instruments Dual-Single Socket CardBus and UntraMedia Controller PCI7621 User Manual

Size:
1.32 Mb
Download

8 OHCI Registers

The OHCI registers defined by the 1394 Open Host Controller Interface Specification arememory-mappedinto a2K-byteregion of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 7.8). These registers are the primary interface for controlling the PCI7x21/PCI7x11 IEEE 1394 link function.

This section provides the register interface and bit descriptions. Several set/clear register pairs in this programming model are implemented to solve various issues with typical read-modify-writecontrol registers. There are two addresses for a set/clear register: RegisterSet and RegisterClear. See Table 8−1 for a register listing. A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set to 1; a 0 bit leaves the corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register to be cleared; a 0 bit leaves the corresponding bit in the set/clear register unaffected.

Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively. However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt event register is an example of this behavior.

Table 8−1. OHCI Register Map

DMA CONTEXT

REGISTER NAME

ABBREVIATION

OFFSET

 

 

 

 

 

 

OHCI version

Version

00h

 

 

 

 

 

 

 

GUID ROM

GUID_ROM

04h

 

 

 

 

 

 

 

Asynchronous transmit retries

ATRetries

08h

 

 

 

 

 

 

 

CSR data

CSRData

0Ch

 

 

 

 

 

 

 

CSR compare

CSRCompareData

10h

 

 

 

 

 

 

 

CSR control

CSRControl

14h

 

 

 

 

 

 

 

Configuration ROM header

ConfigROMhdr

18h

 

 

 

 

 

 

 

Bus identification

BusID

1Ch

 

 

 

 

 

 

 

Bus options ‡

BusOptions

20h

 

 

 

 

 

 

 

GUID high ‡

GUIDHi

24h

 

GUID low ‡

GUIDLo

 

28h

 

 

 

 

 

 

 

 

Reserved

 

2Ch−30h

 

 

 

 

 

 

 

 

Configuration ROM mapping

ConfigROMmap

 

34h

 

Posted write address low

PostedWriteAddressLo

 

38h

 

 

 

 

 

 

 

 

Posted write address high

PostedWriteAddressHi

 

3Ch

 

 

 

 

 

 

 

 

Vendor ID

VendorID

 

40h

 

 

 

 

 

 

 

 

Reserved

 

44h−4Ch

 

 

 

HCControlSet

 

50h

 

 

Host controller control ‡

 

 

 

 

 

 

 

 

HCControlClr

 

54h

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

58h−5Ch

 

 

 

 

 

 

One or more bits in this register are cleared only by the assertion of GRST.

8−1

Table 8−1. OHCI Register Map (Continued)

DMA CONTEXT

REGISTER NAME

ABBREVIATION

OFFSET

Self-ID

Reserved

 

60h

 

 

 

 

 

 

Self-IDbuffer pointer

SelfIDBuffer

 

64h

 

 

 

 

 

 

Self-IDcount

SelfIDCount

 

68h

 

 

 

 

 

 

Reserved

 

6Ch

 

 

 

 

 

Isochronous receive channel mask high

IRChannelMaskHiSet

 

70h

 

 

 

 

 

IRChannelMaskHiClear

 

74h

 

 

 

 

Isochronous receive channel mask low

IRChannelMaskLoSet

 

78h

 

 

 

 

 

IRChannelMaskLoClear

 

7Ch

 

 

 

 

 

 

 

 

 

Interrupt event

IntEventSet

 

80h

 

 

 

 

 

IntEventClear

 

84h

 

 

 

 

Interrupt mask

IntMaskSet

 

88h

 

 

 

 

 

IntMaskClear

 

8Ch

 

 

 

 

Isochronous transmit interrupt event

IsoXmitIntEventSet

 

90h

 

 

 

 

 

IsoXmitIntEventClear

 

94h

 

 

 

 

 

IsoXmitIntMaskSet

 

98h

 

Isochronous transmit interrupt mask

 

 

 

 

 

 

IsoXmitIntMaskClear

 

9Ch

 

 

 

Isochronous receive interrupt event

IsoRecvIntEventSet

 

A0h

 

 

 

 

 

IsoRecvIntEventClear

 

A4h

 

 

 

 

 

 

 

 

 

Isochronous receive interrupt mask

IsoRecvIntMaskSet

 

A8h

 

 

 

 

 

IsoRecvIntMaskClear

 

ACh

 

 

 

 

 

 

 

 

 

Initial bandwidth available

InitialBandwidthAvailable

 

B0h

 

 

 

 

 

 

Initial channels available high

InitialChannelsAvailableHi

 

B4h

 

 

 

 

 

 

Initial channels available low

InitialChannelsAvailableLo

 

B8h

 

 

 

 

 

 

Reserved

 

BCh−D8h

 

 

 

 

 

 

Fairness control

FairnessControl

 

DCh

 

 

 

 

 

 

Link control ‡

LinkControlSet

 

E0h

 

 

 

 

 

LinkControlClear

 

E4h

 

 

 

 

 

 

 

 

 

Node identification

NodeID

 

E8h

 

 

 

 

 

 

PHY layer control

PhyControl

 

ECh

 

 

 

 

 

 

Isochronous cycle timer

Isocyctimer

 

F0h

 

 

 

 

 

 

Reserved

 

F4h−FCh

 

 

 

 

 

 

Asynchronous request filter high

AsyncRequestFilterHiSet

 

100h

 

AsyncRequestFilterHiClear

 

104h

 

 

 

 

Asynchronous request filter low

AsyncRequestFilterLoSet

 

108h

 

 

 

 

 

AsyncRequestFilterLoClear

 

10Ch

 

 

 

 

Physical request filter high

PhysicalRequestFilterHiSet

 

110h

 

 

 

 

 

PhysicalRequestFilterHiClear

 

114h

 

 

 

 

 

PhysicalRequestFilterLoSet

 

118h

 

Physical request filter low

 

 

 

 

 

 

PhysicalRequestFilterLoClear

 

11Ch

 

 

 

 

Physical upper bound

PhysicalUpperBound

 

120h

 

 

 

 

 

 

Reserved

 

124h−17Ch

 

 

 

 

 

One or more bits in this register are cleared only by the assertion of GRST.

8−2

Table 8−1. OHCI Register Map (Continued)

DMA CONTEXT

REGISTER NAME

ABBREVIATION

OFFSET

 

 

 

 

 

 

 

Asynchronous context control

ContextControlSet

180h

 

 

 

 

 

Asynchronous

ContextControlClear

184h

 

Request Transmit

Reserved

 

188h

[ ATRQ ]

Asynchronous context command pointer

CommandPtr

 

18Ch

 

 

 

 

 

 

 

 

Reserved

 

190h−19Ch

 

 

 

 

 

 

 

 

Asynchronous context control

ContextControlSet

 

1A0h

 

 

 

 

 

 

Asynchronous

ContextControlClear

 

1A4h

 

 

 

 

Response Transmit

Reserved

 

1A8h

 

[ ATRS ]

Asynchronous context command pointer

CommandPtr

 

1ACh

 

 

 

 

 

 

 

 

Reserved

 

1B0h−1BCh

 

 

 

 

 

 

 

 

Asynchronous context control

ContextControlSet

 

1C0h

 

 

 

 

 

 

Asynchronous

ContextControlClear

 

1C4h

 

 

 

 

Request Receive

Reserved

 

1C8h

 

[ ARRQ ]

 

 

 

 

 

Asynchronous context command pointer

CommandPtr

 

1CCh

 

 

 

 

 

 

 

 

Reserved

 

1D0h−1DCh

 

 

 

 

 

 

 

 

Asynchronous context control

ContextControlSet

 

1E0h

 

 

 

 

 

 

Asynchronous

ContextControlClear

 

1E4h

 

 

 

 

Response Receive

Reserved

 

1E8h

 

[ ARRS ]

 

 

 

 

 

Asynchronous context command pointer

CommandPtr

 

1ECh

 

 

 

 

 

 

 

 

Reserved

 

1F0h−1FCh

 

 

 

 

 

 

 

 

Isochronous transmit context control

ContextControlSet

 

200h + 16*n

 

 

 

 

 

 

Isochronous

ContextControlClear

204h + 16*n

 

Reserved

 

208h + 16*n

 

Transmit Context n

 

 

 

 

 

 

 

Isochronous transmit context command

 

 

 

 

n = 0, 1, 2, 3, , 7

CommandPtr

 

20Ch + 16*n

 

pointer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

210h−3FCh

 

Isochronous receive context control

ContextControlSet

 

400h + 32*n

Isochronous

ContextControlClear

 

404h + 32*n

 

 

 

 

Reserved

 

408h + 32*n

 

Receive Context n

 

 

 

 

 

 

 

Isochronous receive context command

 

 

 

 

n = 0, 1, 2, 3

CommandPtr

 

40Ch + 32*n

 

pointer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Isochronous receive context match

ContextMatch

410h + 32*n

 

 

 

 

 

 

8−3

8.1 OHCI Version Register

The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See Table 8−2 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

OHCI version

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

RU

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

X

0

0

0

0

0

0

0

1

Bit

15

 

14

13

12

 

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

OHCI version

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

 

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

 

0

0

0

0

0

0

0

1

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

OHCI version

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0X01 0010h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 8−2. OHCI Version Register Description

BIT

FIELD NAME

TYPE

 

DESCRIPTION

 

 

 

 

 

31−25

RSVD

R

 

Reserved. Bits 31−25 return 0s when read.

 

 

 

 

 

24 ‡

GUID_ROM

RU

 

The PCI7x21/PCI7x11 controller sets bit 24 to 1 if the serial EEPROM is detected. If the serial

 

 

 

 

EEPROM is present, then the Bus_Info_Block is automatically loaded on system (hardware) reset.

 

 

 

 

The default value for this bit is 0.

 

 

 

 

 

23−16

version

R

 

Major version of the OHCI. The PCI7x21/PCI7x11 controller is compliant with the 1394 Open Host

 

 

 

 

Controller Interface Specification (Release 1.1); thus, this field reads 01h.

 

 

 

 

 

15−8

RSVD

R

 

Reserved. Bits 15−8 return 0s when read.

 

 

 

 

 

7−0

revision

R

 

Minor version of the OHCI. The PCI7x21/PCI7x11 controller is compliant with the 1394 Open Host

 

 

 

 

Controller Interface Specification (Release 1.1); thus, this field reads 10h.

 

 

 

 

 

This bit is cleared only by the assertion of GRST.

8−4

8.2 GUID ROM Register

The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register at OHCI offset 00h (see Section 8.1) is set to 1. See Table 8−3 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

GUID ROM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RSU

R

R

R

R

R

RSU

R

RU

RU

RU

RU

RU

RU

RU

RU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

X

X

X

X

X

X

X

X

Bit

15

 

14

13

12

 

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

GUID ROM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

 

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

 

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

GUID ROM

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

04h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Set/Update, Read/Update, Read-only

 

 

 

 

 

 

 

 

Default:

 

00XX 0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 8−3. GUID ROM Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

 

 

 

 

31

addrReset

RSU

Software sets bit 31 to 1 to reset the GUID ROM address to 0. When the PCI7x21/PCI7x11 controller

 

 

 

completes the reset, it clears this bit. The PCI7x21/PCI7x11 controller does not automatically fill bits

 

 

 

23−16 (rdData field) with the 0 th byte.

30−26

RSVD

R

Reserved. Bits 30−26 return 0s when read.

 

 

 

 

25

rdStart

RSU

A read of the currently addressed byte is started when bit 25 is set to 1. This bit is automatically cleared

 

 

 

when the PCI7x21/PCI7x11 controller completes the read of the currently addressed GUID ROM byte.

 

 

 

 

24

RSVD

R

Reserved. Bit 24 returns 0 when read.

 

 

 

 

23−16

rdData

RU

This field contains the data read from the GUID ROM.

 

 

 

 

15−8

RSVD

R

Reserved. Bits 15−8 return 0s when read.

 

 

 

 

7−0

miniROM

R

The miniROM field defaults to 00h indicating that no mini-ROMis implemented. If an EEPROM is

 

 

 

implemented, then all 8 bits of this miniROM field are downloaded from EEPROM word offset 28h. For

 

 

 

this device, the miniROM field must be greater than ??h to indicate a valid miniROM offset into the

 

 

 

EEPROM.

 

 

 

 

8−5

8.3 Asynchronous Transmit Retries Register

The asynchronous transmit retries register indicates the number of times the PCI7x21/PCI7x11 controller attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 8−4 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

Asynchronous transmit retries

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

13

 

12

11

10

9

 

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

Asynchronous transmit retries

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

 

RW

RW

RW

 

RW

RW

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

0

0

0

 

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Asynchronous transmit retries

 

 

 

 

 

 

 

 

 

 

 

Offset:

08h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 8−4. Asynchronous Transmit Retries Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

31−29

 

 

secondLimit

 

R

 

The second limit field returns 0s when read, because outbound dual-phaseretry is not

 

 

 

 

 

 

 

 

 

implemented.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28−16

 

 

cycleLimit

 

 

R

 

The cycle limit field returns 0s when read, because outbound dual-phaseretry is not implemented.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15−12

 

 

 

RSVD

 

 

R

 

Reserved. Bits 15−12 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

11−8

 

maxPhysRespRetries

 

RW

 

This field tells the physical response unit how many times to attempt to retry the transmit operation

 

 

 

 

 

 

 

 

 

for the response packet when a busy acknowledge or ack_data_error is received from the target

 

 

 

 

 

 

 

 

 

node. The default value for this field is 0h.

 

 

 

 

 

 

 

 

 

 

 

 

 

7−4

 

maxATRespRetries

 

RW

 

This field tells the asynchronous transmit response unit how many times to attempt to retry the

 

 

 

 

 

 

 

 

 

transmit operation for the response packet when a busy acknowledge or ack_data_error is

 

 

 

 

 

 

 

 

 

received from the target node. The default value for this field is 0h.

 

 

 

 

 

 

 

 

 

 

3−0

 

maxATReqRetries

 

RW

 

This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the

 

 

 

 

 

 

 

 

 

transmit operation for the response packet when a busy acknowledge or ack_data_error is

 

 

 

 

 

 

 

 

 

received from the target node. The default value for this field is 0h.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8.4 CSR Data Register

The CSR data register accesses the bus management CSR registers from the host through compare-swapoperations. This register contains the data to be stored in a CSR if the compare is successful.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

CSR data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Bit

15

 

14

13

12

 

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

CSR data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

 

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

 

X

X

X

 

X

X

X

X

X

X

X

X

X

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

CSR data

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

0Ch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

XXXX XXXXh

 

 

 

 

 

 

 

 

 

 

 

 

8−6

8.5 CSR Compare Register

The CSR compare register accesses the bus management CSR registers from the host through compare-swapoperations. This register contains the data to be compared with the existing value of the CSR resource.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

CSR compare

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Bit

15

 

14

13

12

 

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

CSR compare

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

 

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

 

X

X

X

 

X

X

X

X

X

X

X

X

X

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

CSR compare

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

10h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

XXXX XXXXh

 

 

 

 

 

 

 

 

 

 

 

 

8.6 CSR Control Register

The CSR control register accesses the bus management CSR registers from the host through compare-swapoperations. This register controls thecompare-swapoperation and selects the CSR resource. See Table 8−5 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

CSR control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RU

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

13

12

 

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

CSR control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

 

R

R

R

R

R

R

R

R

R

R

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

 

0

0

0

0

0

0

0

0

0

0

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

CSR control

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

14h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Write, Read/Update, Read-only

 

 

 

 

 

 

 

 

 

Default:

 

8000 000Xh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 8−5. CSR Control Register Description

BIT

FIELD NAME

TYPE

 

DESCRIPTION

 

 

 

 

31

csrDone

RU

Bit 31 is set to 1 by the PCI7x21/PCI7x11 controller when a compare-swapoperation is complete. It

 

 

 

is cleared whenever this register is written.

 

 

 

 

30−2

RSVD

R

Reserved. Bits 30−2 return 0s when read.

 

 

 

 

1−0

csrSel

RW

This field selects the CSR resource as follows:

 

 

 

00

= BUS_MANAGER_ID

 

 

 

01

= BANDWIDTH_AVAILABLE

 

 

 

10

= CHANNELS_AVAILABLE_HI

 

 

 

11 = CHANNELS_AVAILABLE_LO

 

 

 

 

 

8−7

8.7 Configuration ROM Header Register

The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 8−6 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

Configuration ROM header

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

 

13

 

12

 

 

11

10

9

8

7

 

6

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

Configuration ROM header

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

 

RW

 

RW

 

RW

 

RW

RW

RW

RW

RW

 

RW

RW

RW

 

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

 

X

 

 

X

 

X

 

X

X

X

X

X

 

X

X

X

 

X

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Configuration ROM header

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

 

18h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

 

Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0000 XXXXh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 8−6. Configuration ROM Header Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31−24

 

info_length

 

 

RW

 

IEEE 1394 bus-managementfield. Must be valid when bit 17 (linkEnable) in the host controller control

 

 

 

 

 

 

 

 

 

 

 

register at OHCI offset 50h/54h (see Section 8.16) is set to 1. The default value for this field is 00h.

 

 

 

 

 

 

 

 

23−16

 

crc_length

 

 

RW

 

IEEE 1394 bus-managementfield. Must be valid when bit 17 (linkEnable) in the host controller control

 

 

 

 

 

 

 

 

 

 

 

register at OHCI offset 50h/54h (see Section 8.16) is set to 1. The default value for this field is 00h.

 

 

 

 

 

 

 

 

15−0

 

rom_crc_value

 

 

RW

 

IEEE 1394 bus-managementfield. Must be valid at any time bit 17 (linkEnable) in the host controller

 

 

 

 

 

 

 

 

 

 

 

control register at OHCI offset 50h/54h (see Section 8.16) is set to 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8.8 Bus Identification Register

The bus identification register externally maps to the first quadlet in the Bus_Info_Block and contains the constant 3133 3934h, which is the ASCII value of 1394.

Bit

31

30

29

28

27

26

25

 

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Bus identification

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

 

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

1

1

0

0

0

 

1

0

0

1

1

0

0

1

1

Bit

15

 

14

13

12

11

 

10

9

 

8

7

 

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

Bus identification

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

R

 

R

R

 

R

R

 

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

1

1

1

 

0

0

 

1

0

 

0

1

1

0

1

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Bus identification

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

1Ch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

3133 3934h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8−8

8.9 Bus Options Register

The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 8−7 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Bus options

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

RW

RW

RW

R

R

R

RW

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

X

X

X

0

0

0

0

X

X

X

X

X

X

X

X

Bit

15

 

14

13

12

 

11

10

9

8

 

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

Bus options

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

 

RW

 

RW

 

RW

 

R

R

R

R

 

RW

RW

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

1

 

0

1

0

 

0

0

0

0

 

X

X

0

0

0

0

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

 

Bus options

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

20h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

X0XX A0X2h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 8−7. Bus Options Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

31

 

irmc

 

RW

 

Isochronous resource-managercapable. IEEE 1394bus-managementfield. Must be valid when bit 17

 

 

 

 

 

 

 

(linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1.

 

 

 

 

 

 

 

The default value for this bit is 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30

 

cmc

 

RW

 

Cycle master capable. IEEE 1394 bus-managementfield. Must be valid when bit 17 (linkEnable) in the

 

 

 

 

 

 

 

host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. The default value for

 

 

 

 

 

 

 

this bit is 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

29

 

isc

 

RW

 

Isochronous support capable. IEEE 1394 bus-managementfield. Must be valid when bit 17 (linkEnable)

 

 

 

 

 

 

 

in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. The default

 

 

 

 

 

 

 

value for this bit is 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

 

bmc

 

RW

 

Bus manager capable. IEEE 1394 bus-managementfield. Must be valid when bit 17 (linkEnable) in the

 

 

 

 

 

 

 

host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. The default value for

 

 

 

 

 

 

 

this bit is 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27

 

pmc

 

RW

 

Power-managementcapable. IEEE 1394bus-managementfield. When bit 27 is set to 1, this indicates that

 

 

 

 

 

 

 

the node is power-managementcapable. Must be valid when bit 17 (linkEnable) in the host controller

 

 

 

 

 

 

 

control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. The default value for this bit is 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

26−24

RSVD

 

R

 

Reserved. Bits 26−24 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

23−16

cyc_clk_acc

 

RW

 

Cycle master clock accuracy, in parts per million. IEEE 1394 bus-managementfield. Must be valid when

 

 

 

 

 

 

 

bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set

 

 

 

 

 

 

 

to 1. The default value for this field is 00h.

 

 

 

 

 

 

 

 

 

 

 

 

 

15−12 ‡

max_rec

 

RW

 

Maximum request. IEEE 1394 bus-managementfield. Hardware initializes this field to indicate the

 

 

 

 

 

 

 

maximum number of bytes in a block request packet that is supported by the implementation. This value,

 

 

 

 

 

 

 

max_rec_bytes, must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may change this

 

 

 

 

 

 

 

field; however, this field must be valid at any time bit 17 (linkEnable) in the host controller control register

 

 

 

 

 

 

 

at OHCI offset 50h/54h (see Section 8.16) is set to 1. A received block write request packet with a length

 

 

 

 

 

 

 

greater than max_rec_bytes may generate an ack_type_error. This field is not affected by a software reset,

 

 

 

 

 

 

 

and defaults to value indicating 2048 bytes on a system (hardware) reset. The default value for this field

 

 

 

 

 

 

 

is Ah.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11−8

RSVD

 

R

 

Reserved. Bits 11−8 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7−6

 

g

 

RW

 

Generation counter. This field is incremented if any portion of the configuration ROM has been

 

 

 

 

 

 

 

incremented since the prior bus reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5−3

RSVD

 

R

 

Reserved. Bits 5−3 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2−0

Lnk_spd

 

R

 

Link speed. This field returns 010, indicating that the link speeds of 100M bits/s, 200M bits/s, and

 

 

 

 

 

 

 

400M bits/s are supported.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

These bits are cleared only by the assertion of GRST.

8−9

8.10 GUID High Register

The GUID high register represents the upper quadlet in a 64-bitglobal unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a GRST. At that point, the contents of this register cannot be changed. If no serial EEPROM is detected, then the contents of this register are loaded by the BIOS. At that point, the contents of this register cannot be changed. All bits in this register are reset by GRST only.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

GUID high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

GUID high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

GUID high

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

24h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

8.11 GUID Low Register

The GUID low register represents the lower quadlet in a 64-bitglobal unique ID (GUID) which maps to chip_ID_lo in the Bus_Info_Block. This register initializes to 0s on a system (hardware) reset and behaves identical to the GUID high register at OHCI offset 24h (see Section 8.10). All bits in this register are reset by GRST only.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

GUID low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

GUID low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

GUID low

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

28h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

8−10