Texas Instruments Dual-Single Socket CardBus and UntraMedia Controller PCI7621, Dual-Single Socket CardBus and UntraMedia Controller PCI7411, Dual-Single Socket CardBus and UntraMedia Controller PCI7421, Dual-Single Socket CardBus and UntraMedia Controller PCI7611 User Manual

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7.16 Minimum Grant and Maximum Latency Register

The minimum grant and maximum latency register communicates to the system the desired setting of bits 15−8 in the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 7.6). If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a GRST. If no serial EEPROM is detected, then this register returns a default value that corresponds to the MAX_LAT = 4, MIN_GNT = 2. See Table 7−13 for a complete description of the register contents.

 

Bit

 

15

 

14

 

13

 

 

12

 

11

 

10

 

9

8

7

6

 

5

4

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

Minimum grant and maximum latency

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

 

RU

 

RU

RU

 

 

RU

 

RU

 

RU

 

RU

RU

RU

RU

 

RU

RU

RU

 

RU

RU

RU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

 

0

 

0

 

0

 

 

0

 

0

 

1

 

0

0

0

0

 

0

0

0

 

0

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Minimum grant and maximum latency

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

 

3Eh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

 

Read/Update

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0402h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−13. Minimum Grant and Maximum Latency Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level

 

15−8 ‡

 

MAX_LAT

 

RU

 

to the PCI7x21/PCI7x11 controller. The default for this register indicates that the PCI7x21/PCI7x11

 

 

 

 

controller may need to access the PCI bus as often as every 0.25

s; thus, an extremely high priority level

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is requested. Bits 11−8 of this field may also be loaded through the serial EEPROM.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value

 

 

 

 

 

 

 

 

 

 

to the PCI7x21/PCI7x11 controller. The default for this register indicates that the PCI7x21/PCI7x11

 

7−0 ‡

 

MIN_GNT

 

RU

 

controller may need to sustain burst transfers for nearly 64 s and thus request a large value be

 

 

 

 

programmed in bits 15−8 of the PCI7x21/PCI7x11 latency timer and class cache line size register at offset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0Ch in the PCI configuration space (see Section 7.6). Bits 3−0 of

this field may also be loaded through the

 

 

 

 

 

 

 

 

 

 

serial EEPROM.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

These bits are cleared only by the assertion of GRST.

7.17 OHCI Control Register

The PCI OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support. See Table 7−14 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

OHCI control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

 

13

 

12

 

11

10

9

8

7

 

6

5

 

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

OHCI control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

 

R

 

R

 

R

R

R

R

R

 

R

R

 

R

 

R

R

R

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

 

0

 

0

0

0

0

0

 

0

0

 

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

OHCI control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

 

40h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

 

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

 

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−14. OHCI Control Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

 

TYPE

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31−1

 

RSVD

 

 

R

Reserved. Bits 31−1 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

GLOBAL_SWAP

 

 

RW

When bit 0 is set to 1, all quadlets read from and written to the PCI interface are byte-swapped(big

 

 

 

endian). The default value for this bit is 0 which is little endian mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7−11

7.18 Capability ID and Next Item Pointer Registers

The capability ID and next item pointer register identifies the linked-listcapability item and provides a pointer to the next capability item. See Table 7−15 for a complete description of the register contents.

Bit

15

 

14

13

 

12

11

10

 

9

8

7

6

 

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

Capability ID and next item pointer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

 

R

R

R

 

R

R

R

R

 

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

0

0

 

0

0

0

0

 

0

0

0

0

0

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Capability ID and next item pointer

 

 

 

 

 

 

 

 

 

 

Offset:

 

44h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0001h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−15. Capability ID and Next Item Pointer Registers Description

BIT

FIELD NAME

TYPE

DESCRIPTION

 

 

 

 

 

 

 

Next item pointer. The PCI7x21/PCI7x11 controller supports only one additional capability that is

15−8

NEXT_ITEM

R

communicated to the system through the extended capabilities list; therefore, this field returns 00h

 

 

 

when read.

 

 

 

 

7−0

CAPABILITY_ID

R

Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI

SIG for PCI power-managementcapability.

 

 

 

 

 

 

 

7−12

7.19 Power Management Capabilities Register

The power management capabilities register indicates the capabilities of the PCI7x21/PCI7x11 controller related to PCI power management. See Table 7−16 for a complete description of the register contents.

Bit

15

 

14

13

 

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

Power management capabilities

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RU

 

R

R

 

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

1

1

 

1

1

1

1

0

0

0

0

0

0

0

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Power management capabilities

 

 

 

 

 

 

 

 

 

Offset:

 

46h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Update, Read-only

 

 

 

 

 

 

 

 

 

 

 

Default:

 

7E02h

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−16. Power Management Capabilities Register Description

BIT

FIELD NAME

TYPE

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PME

support from D3cold. This bit can be set to 1 or cleared to 0 via bit 15 (PME_D3COLD) in the PCI

 

 

 

 

miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 7.23).

15

PME_D3COLD

RU

 

The PCI miscellaneous configuration register is loaded from ROM. When this bit is set to 1, it indicates

 

that the PCI7x21/PCI7x11 controller is capable of generating a PME wake event from D3cold. This bit

 

 

 

 

 

 

 

 

state is dependent upon the PCI7x21/PCI7x11 VAUX implementation and may be configured by using

 

 

 

 

bit 15 (PME_D3COLD) in the PCI miscellaneous configuration register (see Section 7.23).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PME

support. This4-bitfield indicates the power states from which the PCI7x21/PCI7x11 controller

14−11

PME_SUPPORT

R

 

may assert PME. This field returns a value of 1111b by default, indicating that PME may be asserted

 

 

 

 

from the D3hot, D2, D1, and D0 power states.

10

D2_SUPPORT

R

 

D2 support. Bit 10 is hardwired to 1, indicating that the PCI7x21/PCI7x11 controller supports the D2

 

power state.

 

 

 

 

 

 

 

 

 

9

D1_SUPPORT

R

 

D1 support. Bit 9 is hardwired to 1, indicating that the PCI7x21/PCI7x11 controller supports the D1

 

power state.

 

 

 

 

 

 

 

 

 

 

 

 

 

Auxiliary current. This 3-bitfield reports the3.3-VAUX auxiliary current requirements. When bit 15

8−6

AUX_CURRENT

R

 

(PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b.

 

000b = Self-powered

 

 

 

 

 

 

 

 

001b = 55 mA (3.3-VAUX maximum current required)

 

 

 

 

Device-specificinitialization. This bit returns 0 when read, indicating that the PCI7x21/PCI7x11

5

DSI

R

 

controller does not require special initialization beyond the standard PCI configuration header before

 

 

 

 

a generic class driver is able to use it.

 

 

 

 

 

4

RSVD

R

 

Reserved. Bit 4 returns 0 when read.

 

 

 

 

 

 

 

 

 

 

3

PME_CLK

R

 

PME

clock. This bit returns 0 when read, indicating that no host bus clock is required for the

 

PCI7x21/PCI7x11 controller to generate PME.

 

 

 

 

 

 

 

 

 

 

 

 

 

Power-managementversion. This field returns 010b when read, indicating that the PCI7x21/PCI7x11

2−0

PM_VERSION

R

 

controller is compatible with the registers described in the PCI Bus Power Management Interface

 

 

 

 

Specification (Revision 1.1).

 

 

 

 

 

 

7−13

7.20 Power Management Control and Status Register

The power management control and status register implements the control and status of the PCI power-managementfunction. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 7−17 for a complete description of the register contents.

Bit

15

 

14

 

13

 

12

 

11

10

9

 

8

7

 

6

 

5

4

3

 

 

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

Power management control and status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RWC

 

R

 

R

 

R

 

R

R

 

R

RW

R

 

R

 

R

R

 

R

 

R

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

 

0

 

0

0

0

 

0

0

 

0

 

0

0

0

 

 

 

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Power management control and status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

 

48h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

 

Read/Clear, Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

 

0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−17. Power Management Control and Status Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit 15 is set to 1 when the PCI7x21/PCI7x11 controller normally asserts the

PME

signal independent

15 ‡

 

PME_STS

 

RWC

 

of the state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, which also clears the PME signal

 

 

 

 

 

 

 

 

 

 

driven by the PCI7x21/PCI7x11 controller. Writing a 0 to this bit has no effect.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14−13

 

DATA_SCALE

 

R

 

This field returns 0s, because the data register is not implemented.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12−9

 

DATA_SELECT

 

R

 

This field returns 0s, because the data register is not implemented.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When bit 8 is set to 1,

PME

assertion is enabled. When bit 8 is cleared,

PME

assertion is disabled. This

8 ‡

 

PME_ENB

 

RW

 

bit defaults to 0 if the function does not support PME generation from D3cold. If the function supports

 

 

 

PME from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

time it is initially loaded.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7−2

 

RSVD

 

R

 

Reserved. Bits 7−2 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power state. This 2-bitfield sets the PCI7x21/PCI7x11 controller power state and is encoded as

 

 

 

 

 

 

 

 

 

 

follows:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1−0 ‡

 

PWR_STATE

 

RW

 

 

00 = Current power state is D0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

01 = Current power state is D1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10 = Current power state is D2.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11 = Current power state is D3.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

These bits are cleared only by the assertion of GRST.

7.21 Power Management Extension Registers

The power management extension register provides extended power-managementfeatures not applicable to the PCI7x21/PCI7x11 controller; thus, it isread-onlyand returns 0 when read. See Table 7−18 for a complete description of the register contents.

Bit

15

 

14

13

 

12

 

 

11

10

9

 

8

7

 

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

Power management extension

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

 

R

 

R

R

R

 

R

R

 

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

 

 

0

0

0

 

0

0

 

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Power management extension

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

4Ah

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−18. Power Management Extension Registers Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15−0

 

RSVD

 

R

 

 

Reserved. Bits 15−0 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7−14

7.22 PCI PHY Control Register

The PCI PHY control register provides a method for enabling the PHY CNA output. See Table 7−19 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

PCI PHY control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

 

13

 

12

 

11

 

10

9

8

7

6

5

4

3

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI PHY control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

 

R

 

R

 

R

 

R

R

R

RW

R

R

RW

RW

RW

 

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

 

 

0

 

0

 

0

0

0

0

0

0

0

1

0

 

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

PCI PHY control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

ECh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0000 0008h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−19. PCI PHY Control Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

 

TYPE

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31−8

 

 

RSVD

 

 

 

R

Reserved. Bits 31−8 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7 ‡

 

 

CNAOUT

 

 

RW

When bit 7 is set to 1, the PHY CNA output is routed to terminal P18. When implementing a serial

 

 

 

 

 

 

 

 

 

 

EEPROM, this bit is loaded via the serial EEPROM as defined by Table 3−9 and must be 1 for normal

 

 

 

 

 

 

 

 

 

 

operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6−5

 

 

RSVD

 

 

 

R

Reserved. Bits 6−5 return 0s when read. These bits must be 0s for normal operation.

 

 

 

 

 

 

 

 

 

 

4 ‡

 

 

PHYRST

 

 

RW

PHY reset. This bit controls the RST input to the PHY. When bit 4 is set, the PHY reset is asserted.

 

 

 

 

 

 

 

 

 

 

The default value is 0. This bit must be 0 for normal operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

3 ‡

 

 

RSVD

 

 

RW

Reserved. Bit 3 defaults to 1 to indicate compliance with IEEE Std 1394a-2000.This bit is loaded via

 

 

 

 

 

 

 

 

 

 

the serial EEPROM as defined by Table 3−9 and must be 1 for normal operation.

 

 

 

 

 

 

 

 

 

 

 

2 ‡

 

 

 

PD

 

 

RW

This bit controls the power-downinput to the PHY. When bit 2 is set, the PHY is in thepower-down

 

 

 

 

 

 

 

 

 

 

mode and enters the ULP mode if the LPS is disabled. If PD is asserted, then a reset to the physical

 

 

 

 

 

 

 

 

 

 

layer must be initiated via bit 4 (PHYRST) after PD is cleared. The default value is 0. This bit must

 

 

 

 

 

 

 

 

 

 

be 0 for normal operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1−0 ‡

 

 

RSVD

 

 

RW

Reserved. Bits 1−0 return 0s when read. These bits are affected when implementing a serial

 

 

 

 

 

 

 

 

 

 

EEPROM; thus, bits 1−0 are loaded via the serial EEPROM as defined by Table 3−9 and must be

 

 

 

 

 

 

 

 

 

 

0s for normal operation.

 

 

 

 

 

 

 

 

 

 

These bits are cleared only by the assertion of GRST.

7−15

7.23 PCI Miscellaneous Configuration Register

The PCI miscellaneous configuration register provides miscellaneous PCI-relatedconfiguration. See Table 7−20 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

PCI miscellaneous configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

PCI miscellaneous configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

 

R

RW

R

RW

RW

RW

RW

R

R

R

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

PCI miscellaneous configuration

 

 

 

 

 

 

 

 

 

Offset:

 

F0h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−20. PCI Miscellaneous Configuration Register Description

BIT

FIELD NAME

TYPE

 

 

DESCRIPTION

 

 

 

 

 

 

31−16

RSVD

R

 

Reserved. Bits 31−16 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

15 ‡

PME_D3COLD

RW

 

PME

support from D3cold. This bit programs bit 15 (PME_D3COLD) in the power management

 

capabilities register at offset 46h in the PCI configuration space (see Section 7.19).

 

 

 

 

 

 

 

 

 

14−12

RSVD

R

 

Reserved. Bits 14−12 return 0s when read.

 

 

 

 

 

11 ‡

PCI2_3_EN

RW

 

PCI 2.3 Enable. The PCI7x21/PCI7x11 1394 OHCI function always conforms to the PCI 2.3

 

specification. Therefore, this bit is tied to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

Ignore IntMask.msterIntEnable bit for PME generation. When set, this bit causes the PME generation

 

 

 

 

behavior to be changed as described in Section 3.8. When set, this bit also causes bit 26 of the OHCI

10 ‡

ignore_mstrIntEna

RW

 

vendor ID register at OHCI offset 40h (see Section 8.15) to read 1; otherwise, bit 26 reads 0.

_for_pme

 

0 = PME behavior generated from unmasked interrupt bits and IntMask.masterIntEnable bit

 

 

 

 

 

 

 

 

(default)

 

 

 

 

1 = PME generation does not depend on the value of IntMask.masterIntEnable

 

 

 

 

 

 

 

 

 

This field selects the read command behavior of the PCI master for read transactions of greater than

 

 

 

 

two data phases. For read transactions of one or two data phases, a memory read command is used.

 

 

 

 

The default of this field is 00. This register is loaded by the serial EEPROM word 12, bits 1−0.

9−8 ‡

MR_ENHANCE

RW

 

00 = Memory read line (default)

 

 

 

 

01 = Memory read

 

 

 

 

10 = Memory read multiple

 

 

 

 

11 = Reserved, behavior reverts to default

 

 

 

 

 

7−6

RSVD

R

 

Reserved. Bits 7−6 return 0s when read.

 

 

 

 

 

5 ‡

RSVD

R

 

Reserved. Bit 5 returns 0 when read.

 

 

 

 

 

 

 

 

 

Bit 4 defaults to 0, which provides OHCI-Lynxcompatible target abort signaling. When this bit is

 

 

 

 

set to 1, it enables the no-target-abortmode, in which the PCI7x21/PCI7x11 controller returns

 

 

 

 

indeterminate data instead of signaling target abort.

4 ‡

DIS_TGT_ABT

RW

 

The PCI7x21/PCI7x11 LLC is divided into the PCLK and SCLK domains. If software tries to access

 

registers in the link that are not active because the SCLK is disabled, then a target abort is issued

 

 

 

 

 

 

 

 

by the link. On some systems, this can cause a problem resulting in a fatal system error. Enabling

 

 

 

 

this bit allows the link to respond to these types of requests by returning FFh.

 

 

 

 

It is recommended that this bit be cleared to 0.

 

 

 

 

 

3 ‡

GP2IIC

RW

 

When bit 3 is set to 1, the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA,

 

respectively. The GPIO3 and GPIO2 terminals are also placed in the high-impedancestate.

 

 

 

 

 

 

 

 

 

2 ‡

DISABLE_

RW

 

When bit 2 is set to 1, the internal SCLK runs identically with the chip input. This is a test feature only

SCLKGATE

 

and must be cleared to 0 (all applications).

 

 

 

 

 

 

 

 

 

7−16

Table 7−20. PCI Miscellaneous Configuration Register Description (Continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

 

 

 

 

 

 

1 ‡

DISABLE_

RW

When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test feature

PCIGATE

only and must be cleared to 0 (all applications).

 

 

 

 

 

 

 

 

 

 

 

 

0 ‡

KEEP_PCLK

RW

When bit 0 is set to 1, the PCI clock is always kept running through the

CLKRUN

protocol. When this

bit is cleared, the PCI clock can be stopped using CLKRUN on MFUNC6.

 

 

 

 

 

 

 

 

 

This bit is cleared only by the assertion of GRST.

7.24 Link Enhancement Control Register

The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. See Table 7−21 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

Link enhancement control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

 

15

 

14

 

13

 

12

 

11

10

9

8

 

7

6

 

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

Link enhancement control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

 

RW

 

R

RW

RW

 

R

RW

R

RW

 

RW

R

 

R

R

 

R

R

RW

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

 

0

 

0

 

0

 

1

 

0

 

0

0

0

 

0

0

 

0

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Link enhancement control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

 

F4h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

 

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

 

0000 1000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−21. Link Enhancement Control Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31−16

 

RSVD

 

 

R

 

Reserved. Bits 31−16 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15 ‡

dis_at_pipeline

 

RW

 

Disable AT pipelining. When bit 15 is set to 1, out-of-orderAT pipelining is disabled. The default value for this

 

 

bit is 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14 ‡

 

RSVD

 

 

R

 

Reserved. Bit 14 defaults to 0 and must remain 0 for normal operation of the OHCI core.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the

 

 

 

 

 

 

 

 

PCI7x21/PCI7x11 controller retries the packet, it uses a 2K-bytethreshold, resulting in astore-and-forward

 

 

 

 

 

 

 

 

operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00 = Threshold ~ 2K bytes resulting in a store-and-forwardoperation

 

 

 

 

 

 

 

 

 

 

 

 

01 = Threshold ~ 1.7K bytes (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10 = Threshold ~ 1K bytes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11 = Threshold ~ 512 bytes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

These bits fine-tunethe asynchronous transmit threshold. For most applications the1.7K-bytethreshold is

 

 

 

 

 

 

 

 

optimal. Changing this value may increase or decrease the 1394 latency depending on the average PCI bus

13−12

 

 

 

 

 

 

 

latency.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

atx_thresh

 

RW

 

Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds or

 

 

 

 

 

 

 

 

 

 

when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than the AT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise, an underrun

 

 

 

 

 

 

 

 

condition occurs, resulting in a packet error at the receiving node. As a result, the link then commences a

 

 

 

 

 

 

 

 

store-and-forwardoperation. It waits until it has the complete packet in the FIFO before retransmitting it on

 

 

 

 

 

 

 

 

the second attempt to ensure delivery.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

An AT threshold of 2K results in a store-and-forwardoperation, which means that asynchronous data is not

 

 

 

 

 

 

 

 

transmitted until an end-of-packettoken is received. Restated, setting the AT threshold to 2K results in only

 

 

 

 

 

 

 

 

complete packets being transmitted.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note that this controller always uses a store-and-forwardoperation when the asynchronous transmit retries

 

 

 

 

 

 

 

 

register at OHCI offset 08h (see Section 8.3) is cleared.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

These

bits are cleared only by the assertion of

GRST.

 

 

 

 

 

 

 

 

 

 

 

 

 

7−17

Table 7−21. Link Enhancement Control Register Description (Continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

 

 

 

 

11

RSVD

R

Reserved. Bit 11 returns 0 when read.

 

 

 

 

10 ‡

enab_mpeg_ts

RW

Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is enabled for

MPEG CIP transmit streams (FMT = 20h). The default value for this bit is 0.

 

 

 

 

 

 

 

9

RSVD

R

Reserved. Bit 9 returns 0 when read.

 

 

 

 

8 ‡

enab_dv_ts

RW

Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV

CIP transmit streams (FMT = 00h). The default value for this bit is 0.

 

 

 

 

 

 

 

 

 

 

Enable asynchronous priority requests. OHCI-Lynxcompatible. Setting bit 7 to 1 enables the link to

7 ‡

enab_unfair

RW

respond to requests with priority arbitration. It is recommended that this bit be set to 1. The default value

 

 

 

for this bit is 0.

 

 

 

 

 

 

 

This bit is not assigned in the PCI7x21/PCI7x11 follow-onproducts, because this bit location loaded

6

RSVD

R

by the serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the

 

 

 

host controller control register at OHCI offset 50h/54h (see Section 8.16).

 

 

 

 

5−3

RSVD

R

Reserved. Bits 5−3 return 0s when read.

 

 

 

 

2 ‡

RSVD

R

Reserved. Bit 2 returns 0 when read.

 

 

 

 

 

 

 

Enable acceleration enhancements. OHCI-Lynxcompatible. When bit 1 is set to 1, the PHY layer

1 ‡

enab_accel

RW

is notified that the link supports the IEEE Std 1394a-2000acceleration enhancements, that is,

ack-accelerated,fly-byconcatenation, etc. It is recommended that this bit be set to 1. The default value

 

 

 

 

 

 

for this bit is 0.

 

 

 

 

0

RSVD

R

Reserved. Bit 0 returns 0 when read.

 

 

 

 

This bit is cleared only by the assertion of GRST.

7.25 Subsystem Access Register

Write access to the subsystem access register updates the subsystem identification registers identically to OHCI-Lynx .The system ID value written to this register may also be read back from this register. See Table 7−22 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

 

24

23

 

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Subsystem access

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

RW

RW

RW

RW

RW

 

RW

RW

 

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

 

0

0

 

0

0

0

0

0

0

0

Bit

15

 

14

 

13

 

12

 

11

10

9

 

8

7

 

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

Subsystem access

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

 

RW

 

RW

 

RW

 

RW

RW

RW

 

RW

RW

 

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

 

0

 

0

0

0

 

0

0

 

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Subsystem access

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

 

F8h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

 

Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−22. Subsystem Access Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

FIELD NAME

 

 

TYPE

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31−16 ‡

SUBDEV_ID

 

 

RW

Subsystem device ID alias. This field indicates the subsystem device ID.

 

 

 

 

 

 

 

 

 

 

 

 

15−0 ‡

SUBVEN_ID

 

 

RW

Subsystem vendor ID alias. This field indicates the subsystem vendor ID.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

These bits are cleared only by the assertion of GRST.

7−18

7.26 GPIO Control Register

The GPIO control register has the control and status bits for GPIO0, GPIO1, GPIO2, and GPIO3 ports. Upon reset, GPIO0 and GPIO1 default to bus manager contender (BMC) and link power status terminals, respectively. The BMC terminal can be configured as GPIO0 by setting bit 7 (DISABLE_BMC) to 1. The LPS terminal can be configured as GPIO1 by setting bit 15 (DISABLE_LPS) to 1. See Table 7−23 for a complete description of the register contents.

Bit

31

 

30

29

 

28

 

27

 

26

 

25

 

24

 

23

 

22

21

 

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

 

R/W

 

R/W

 

R

 

R

 

R

 

R/W

 

R

 

R

R/W

 

R/W

R

R

R

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

0

 

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

15

 

14

13

 

12

 

11

 

10

 

9

 

8

 

7

 

6

5

 

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R/W

 

R

 

R/W

 

R/W

 

R

 

R

 

R

 

R/W

 

R/W

 

R

R/W

 

R/W

R

R

R

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

0

 

0

0

0

0

0

 

 

Register:

GPIO control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only,Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

FCh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−23. GPIO Control Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

SIGNAL

 

TYPE

 

 

 

 

 

 

 

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31−30

 

RSVD

 

R

 

Reserved. Bits 31 and 30 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO3 polarity invert. This bit controls the input/output polarity control of GPIO3.

 

 

29

 

GPIO_INV3

 

R/W

 

0

= Noninverted (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

= Inverted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO3 enable control. This bit controls the output enable for GPIO3.

 

 

 

 

28

 

GPIO_ENB3

 

R/W

 

0

= High-impedanceoutput (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

= Output is enabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27−25

 

RSVD

 

R

 

Reserved. Bits 27−25 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

24

 

GPIO_DATA3

 

R/W

 

GPIO3 data. When GPIO3 output is enabled, the value written to this bit represents the logical data

 

 

 

driven to the GPIO3 terminal.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23−22

 

RSVD

 

R

 

Reserved. Bits 23 and 22 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO2 polarity invert. This bit controls the input/output polarity control of GPIO2.

 

 

21

 

GPIO_INV2

 

R/W

 

0

= Noninverted (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

= Inverted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO2 enable control. This bit controls the output enable for GPIO2.

 

 

 

 

20

 

GPIO_ENB2

 

R/W

 

0

= High-impedanceoutput (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

= Output is enabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19−17

 

RSVD

 

R

 

Reserved. Bits 19−17 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

GPIO_DATA2

 

R/W

 

GPIO2 data. When GPIO2 output is enabled, the value written to this bit represents the logical data

 

 

 

driven to the GPIO2 terminal.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Disable link power status (LPS). This bit configures this terminal as

 

 

 

 

15

 

DISABLE_LPS

 

R/W

 

0

= LPS (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

= GPIO1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

RSVD

 

R

 

Reserved. Bit 14 returns 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO1 polarity invert. When bit 15 (DISABLE_LPS) is set to 1, this bit controls the input/output polarity

13

 

GPIO_INV1

 

R/W

 

control of GPIO1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

= Noninverted (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

= Inverted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7−19

Table 7−23. GPIO Control Register Description (Continued)

BIT

SIGNAL

TYPE

 

FUNCTION

 

 

 

 

 

 

 

GPIO1 enable control. When bit 15 (DISABLE_LPS) is set to 1, this bit controls the output enable for

12

GPIO_ENB1

R/W

GPIO1.

0

= High-impedanceoutput (default)

 

 

 

 

 

 

1

= Output is enabled

 

 

 

 

11−9

RSVD

R

Reserved. Bits 11−9 return 0s when read.

 

 

 

 

8

GPIO_DATA1

R/W

GPIO1 data. When bit 15 (DISABLE_LPS) is set to 1 and GPIO1 output is enabled, the value written to

this bit represents the logical data driven to the GPIO1 terminal.

 

 

 

 

 

 

 

 

 

 

Disable bus manager contender (BMC). This bit configures this terminal as bus manager contender or

7

DISABLE_BMC

R/W

GPIO0.

0

= BMC (default)

 

 

 

 

 

 

1

= GPIO0

 

 

 

 

6

RSVD

R

Reserved. Bit 6 returns 0 when read.

 

 

 

 

 

 

 

GPIO0 polarity invert. When bit 7 (DISABLE_BMC) is set to 1, this bit controls the input/output polarity

5

GPIO_INV0

R/W

control for GPIO0.

0

= Noninverted (default)

 

 

 

 

 

 

1

= Inverted

 

 

 

 

 

 

 

GPIO0 enable control. When bit 7 (DISABLE_BMC) is set to 1, this bit controls the output enable for

4

GPIO_ENB0

R/W

GPIO0.

0

= High-impedanceoutput (default)

 

 

 

 

 

 

1

= Output is enabled

 

 

 

 

3−1

RSVD

R

Reserved. Bits 3−1 return 0s when read.

 

 

 

 

0

GPIO_DATA0

R/W

GPIO0 data. When bit 7 (DISABLE_BMC) is set to 1 and GPIO0 output is enabled, the value written to

this bit represents the logical data driven to the GPIO0 terminal.

 

 

 

 

 

 

 

 

7−20