Texas Instruments Dual-Single Socket CardBus and UntraMedia Controller PCI7621 User Manual

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7 OHCI Controller Programming Model

This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 1394 open host controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register.

A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1 describes the field access tags.

The PCI7x21/PCI7x11 controller is a multifunction PCI device. The 1394 OHCI is integrated as PCI function 2. The function 2 configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 7−1 illustrates the configuration header that includes both the predefined portion of the configuration space and theuser-definableregisters.

Table 7−1. Function 2 Configuration Register Map

 

REGISTER NAME

 

OFFSET

 

 

 

 

 

Device ID

Vendor ID

00h

 

 

 

 

 

Status

Command

04h

 

 

 

 

 

 

Class code

 

Revision ID

08h

 

 

 

 

 

BIST

Header type

Latency timer

Cache line size

0Ch

 

 

 

 

 

 

OHCI base address

 

10h

 

 

 

 

 

TI extension base address

 

14h

 

 

 

 

 

CardBus CIS base address

 

18h

 

 

 

 

 

Reserved

 

1Ch−27h

 

 

 

 

 

CardBus CIS pointer ‡

 

28h

 

 

 

Subsystem ID ‡

Subsystem vendor ID ‡

2Ch

 

 

 

 

 

 

Reserved

 

30h

 

 

 

 

 

 

 

 

PCI power

34h

 

Reserved

 

management

 

 

 

 

capabilities pointer

 

 

 

 

 

 

Reserved

 

38h

 

 

 

 

 

Maximum latency ‡

Minimum grant ‡

Interrupt pin

Interrupt line

3Ch

 

 

 

 

 

 

PCI OHCI control

 

40h

 

 

 

 

Power management capabilities

Next item pointer

Capability ID

44h

 

 

 

 

 

PM data

PMCSR_BSE

Power management control and status ‡

48h

 

 

 

 

 

 

Reserved

 

4Ch−EBh

 

 

 

 

 

PCI PHY control ‡

 

ECh

 

 

 

 

 

PCI miscellaneous configuration ‡

 

F0h

 

 

 

 

 

Link enhancement control ‡

 

F4h

 

 

 

 

 

Subsystem access ‡

 

F8h

 

 

 

 

 

GPIO control

 

FCh

 

 

 

 

 

One or more bits in this register are cleared only by the assertion of GRST.

7−1

7.1 Vendor ID Register

The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Vendor ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

1

0

0

0

0

0

1

0

0

1

1

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register: Vendor ID

Offset: 00h

Type: Read-only

Default: 104Ch

7.2 Device ID Register

The device ID register contains a value assigned to the PCI7x21/PCI7x11 controller by Texas Instruments. The device identification for the PCI7x21/PCI7x11 controller is 8032h.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Device ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

1

0

0

0

0

0

0

0

0

0

1

1

0

0

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register: Device ID

Offset: 02h

Type: Read-only

Default: 8032h

7−2

7.3 Command Register

The command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7−2 for a complete description of the register contents.

Bit

15

 

14

 

13

 

12

 

 

11

 

10

9

8

 

7

 

6

5

4

 

3

 

2

1

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Command

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

 

R

 

R

 

 

 

R

 

RW

R

RW

 

R

 

RW

R

 

RW

R

 

RW

 

RW

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

 

0

 

 

0

 

0

0

0

 

0

 

0

0

0

 

0

 

0

0

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Command

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

 

04h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

 

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

 

0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−2. Command Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15−11

 

RSVD

 

R

 

 

Reserved. Bits 15−11 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

signals.

 

 

 

 

 

 

 

 

 

 

 

INTx

disable. When set to 1, this bit disables the function from asserting interrupts on the

INTx

 

10

 

INT_DISABLE

 

RW

 

 

 

0 = INTx assertion is enabled (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 = INTx assertion is disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

FBB_ENB

 

R

 

 

Fast back-to-backenable. The PCI7x21/PCI7x11 controller does not generate fastback-to-back

 

 

 

 

transactions; therefore, bit 9 returns 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

driver is enabled.

 

can be

8

 

SERR_ENB

 

RW

 

 

SERR

enable. When bit 8 is set to 1, the PCI7x21/PCI7x11

SERR

SERR

 

 

 

 

asserted after detecting an address parity error on the PCI bus. The default value for this bit is 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

RSVD

 

R

 

 

Reserved. Bit 7 returns 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

PERR_ENB

 

RW

 

 

Parity error enable. When bit 6 is set to 1, the PCI7x21/PCI7x11 controller is enabled to drive

PERR

 

 

 

 

 

response to parity errors through the PERR signal. The default value for this bit is 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

VGA_ENB

 

R

 

 

VGA palette snoop enable. The PCI7x21/PCI7x11 controller does not feature VGA palette snooping;

 

 

 

 

therefore, bit 5 returns 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory write and invalidate enable. When bit 4 is set to 1, the PCI7x21/PCI7x11 controller is enabled

4

 

MWI_ENB

 

RW

 

 

to generate MWI PCI bus commands. If this bit is cleared, then the PCI7x21/PCI7x11 controller

 

 

 

 

 

 

 

 

 

 

 

generates memory write commands instead. The default value for this bit is 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

SPECIAL

 

R

 

 

Special cycle enable. The PCI7x21/PCI7x11 function does not respond to special cycle transactions;

 

 

 

 

therefore, bit 3 returns 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

MASTER_ENB

 

RW

 

 

Bus master enable. When bit 2 is set to 1, the PCI7x21/PCI7x11 controller is enabled to initiate cycles

 

 

 

 

on the PCI bus. The default value for this bit is 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory response enable. Setting bit 1 to 1 enables the PCI7x21/PCI7x11 controller to respond to

1

 

MEMORY_ENB

 

RW

 

 

memory cycles on the PCI bus. This bit must be set to access OHCI registers. The default value for

 

 

 

 

 

 

 

 

 

 

 

this bit is 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

IO_ENB

 

R

 

 

I/O space enable. The PCI7x21/PCI7x11 controller does not implement any I/O-mappedfunctionality;

 

 

 

 

therefore, bit 0 returns 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7−3

7.4 Status Register

The status register provides status over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7−3 for a complete description of the register contents.

Bit

15

 

14

 

13

 

12

 

11

10

 

9

8

7

 

 

6

 

 

 

5

 

4

 

3

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RCU

 

RCU

 

RCU

 

RCU

RCU

 

R

 

R

RCU

R

 

 

R

 

 

R

R

 

RU

R

 

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

 

0

 

0

0

 

1

0

0

 

 

0

 

 

 

0

 

1

 

0

0

 

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

 

06h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

 

Read/Clear/Update, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0210h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−3. Status Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

PAR_ERR

 

RCU

Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

SYS_ERR

 

RCU

Signaled system error. Bit 14 is set to 1 when

SERR

is enabled and the PCI7x21/PCI7x11 controller

 

 

has signaled a system error to the host.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

MABORT

 

RCU

Received master abort. Bit 13 is set to 1 when a cycle initiated by the PCI7x21/PCI7x11 controller on

 

 

the PCI bus has been terminated by a master abort.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

TABORT_REC

 

RCU

Received target abort. Bit 12 is set to 1 when a cycle initiated by the PCI7x21/PCI7x11 controller on

 

 

the PCI bus was terminated by a target abort.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

TABORT_SIG

 

RCU

Signaled target abort. Bit 11 is set to 1 by the PCI7x21/PCI7x11 controller when it terminates a

 

 

transaction on the PCI bus with a target abort.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEVSEL timing. Bits 10 and 9 encode the timing of

DEVSEL

and are hardwired to 01b, indicating that

10−9

 

PCI_SPEED

 

 

R

the PCI7x21/PCI7x11 controller asserts this signal at a medium speed on nonconfiguration cycle

 

 

 

 

 

 

 

 

 

 

accesses.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data parity error detected. Bit 8 is set to 1 when the following conditions have been met:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

DATAPAR

 

RCU

 

a.

PERR

was asserted by any PCI device including the PCI7x21/PCI7x11 controller.

 

 

 

 

b. The PCI7x21/PCI7x11 controller was the bus master during the data parity error.

 

 

 

 

 

 

 

 

 

 

 

 

 

c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space

 

 

 

 

 

 

 

 

 

 

 

 

 

(see Section 7.3) is set to 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

FBB_CAP

 

 

R

Fast back-to-back

capable. The

PCI7x21/PCI7x11

controller

cannot accept fast

back-to-back

 

 

 

transactions; therefore, bit 7 is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

UDF

 

 

R

User-definablefeatures (UDF) supported. The PCI7x21/PCI7x11 controller does not support the UDF;

 

 

 

therefore, bit 6 is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

66MHZ

 

 

R

66-MHzcapable. The PCI7x21/PCI7x11 controller operates at a maximum PCLK frequency of 33

 

 

 

MHz; therefore, bit 5 is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

CAPLIST

 

 

R

Capabilities list. Bit 4 returns 1 when read, indicating that capabilities additional to standard PCI are

 

 

 

implemented. The linked list of PCI power-managementcapabilities is implemented in this function.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE)

3

 

INT_STATUS

 

 

RU

in the command register (see Section 7.3) is a 0 and this bit is 1, is the function’s INTx signal asserted.

 

 

 

 

 

 

 

 

 

 

Setting the INT_DISABLE bit to 1 has no effect on the state of this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2−0

 

RSVD

 

 

R

Reserved. Bits 3−0 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7−4

7.5 Class Code and Revision ID Register

The class code and revision ID register categorizes the PCI7x21/PCI7x11 controller as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 7−4 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

Class code and revision ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

13

 

12

 

 

11

 

10

9

 

8

 

7

 

6

 

5

 

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

Class code and revision ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

 

R

 

R

 

R

R

 

R

 

R

 

R

 

R

 

R

 

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

1

 

 

0

 

0

0

 

0

 

0

 

0

 

0

 

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Class code and revision ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

08h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0C00 1000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−4. Class Code and Revision ID Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

 

TYPE

 

 

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31−24

 

BASECLASS

 

 

R

 

Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus

 

 

 

 

controller.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23−16

 

SUBCLASS

 

 

R

 

Subclass. This field returns 00h when read, which specifically classifies the function as controlling an

 

 

 

 

IEEE 1394 serial bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15−8

 

PGMIF

 

 

R

 

Programming interface. This field returns 10h when read, which indicates that the programming model

 

 

 

 

is compliant with the 1394 Open Host Controller Interface Specification.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7−0

 

CHIPREV

 

 

R

 

Silicon

revision. This field

returns

00h

when read,

which

indicates

the

silicon

revision

of the

 

 

 

 

PCI7x21/PCI7x11 controller.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7.6 Latency Timer and Class Cache Line Size Register

The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the PCI7x21/PCI7x11 controller. See Table 7−5 for a complete description of the register contents.

 

Bit

 

 

15

 

14

13

 

12

11

10

9

8

7

6

5

4

3

 

2

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

Latency timer and class cache line size

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

 

 

RW

 

RW

 

RW

 

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

 

RW

RW

 

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

 

0

 

0

0

 

0

0

0

0

0

0

0

0

0

0

 

0

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

 

Latency timer and class cache line size

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

 

0Ch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

 

Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−5. Latency Timer and Class Cache Line Size Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI latency timer. The value in this register specifies the latency timer for the PCI7x21/PCI7x11 controller,

 

 

 

 

 

 

 

 

 

 

in units of PCI clock cycles. When the PCI7x21/PCI7x11 controller is a PCI bus initiator and asserts

 

15−8

LATENCY_TIMER

 

RW

FRAME, the

latency timer begins counting from zero. If

the latency timer

expires before the

 

 

 

 

 

 

 

 

 

 

PCI7x21/PCI7x11 transaction has terminated, then the PCI7x21/PCI7x11 controller terminates the

 

 

 

 

 

 

 

 

 

 

transaction when its GNT is deasserted. The default value for this field is 00h.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7−0

 

CACHELINE_SZ

 

RW

Cache line size. This value is used by the PCI7x21/PCI7x11 controller during memory write and invalidate,

 

 

 

memory-readline, andmemory-readmultiple transactions. The default value for this field is 00h.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7−5

7.7 Header Type and BIST Register

The header type and built-inself-test(BIST) register indicates the PCI7x21/PCI7x11 PCI header type and nobuilt-inself-test.See Table 7−6 for a complete description of the register contents.

 

Bit

 

15

 

14

13

 

12

11

10

9

 

8

7

 

6

 

5

4

3

2

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

Header type and BIST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

 

R

 

R

 

R

 

R

R

R

R

 

R

R

 

R

 

R

R

R

R

R

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

 

0

 

0

0

 

0

0

0

0

 

0

1

 

0

 

0

0

0

0

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Header type and BIST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

0Eh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0080h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−6. Header Type and BIST Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15−8

 

BIST

 

 

R

 

Built-inself-test.The PCI7x21/PCI7x11 controller does not include a BIST; therefore, this field returns

 

 

 

 

 

00h when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7−0

HEADER_TYPE

 

R

 

PCI header type. The PCI7x21/PCI7x11 controller

includes the standard PCI header,

which is

 

 

 

communicated by returning 80h when this field is read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7.8 OHCI Base Address Register

The OHCI base address register is programmed with a base address referencing the memory-mappedOHCI control. When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of memory address space are required for the OHCI registers. See Table 7−7 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

 

24

23

 

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

OHCI base address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

RW

RW

RW

RW

RW

 

RW

RW

 

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

 

0

0

 

0

0

0

0

0

0

0

Bit

15

 

14

13

12

11

10

9

 

8

7

 

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

OHCI base address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

 

RW

RW

RW

RW

R

R

 

R

R

 

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

0

0

0

 

0

0

 

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

OHCI base address

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

10h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−7. OHCI Base Address Register Description

BIT

FIELD NAME

TYPE

 

DESCRIPTION

 

 

 

 

31−11

OHCIREG_PTR

RW

OHCI register pointer. This field specifies the upper 21 bits of the 32-bitOHCI base address register.

The default value for this field is all 0s.

 

 

 

 

 

 

 

 

 

10−4

OHCI_SZ

R

OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a

2K-byteregion of memory.

 

 

 

 

 

 

 

 

 

 

3

OHCI_PF

R

OHCI register prefetch. Bit 3 returns

0 when read, indicating that the OHCI registers are

nonprefetchable.

 

 

 

 

 

 

 

 

 

2−1

OHCI_MEMTYPE

R

OHCI memory type. This field returns 0s when read, indicating that the OHCI base address register

is 32 bits wide and mapping can be done anywhere in the 32-bitmemory space.

 

 

 

 

 

 

 

0

OHCI_MEM

R

OHCI memory indicator. Bit 0 returns 0 when read, indicating that the OHCI registers are mapped

into system memory space.

 

 

 

 

 

 

 

 

 

 

7−6

7.9 TI Extension Base Address Register

The TI extension base address register is programmed with a base address referencing the memory-mappedTI extension registers. When BIOS writes all 1s to this register, the value read back is FFFF C000h, indicating that at least 16K bytes of memory address space are required for the TI registers. See Table 7−8 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

TI extension base address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

TI extension base address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

 

RW

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

TI extension base address

 

 

 

 

 

 

 

 

 

 

Offset:

 

14h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

Default:

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−8. TI Base Address Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

 

 

 

 

31−14

TIREG_PTR

RW

TI register pointer. This field specifies the upper 18 bits of the 32-bitTI base address register. The

default value for this field is all 0s.

 

 

 

 

 

 

 

13−4

TI_SZ

R

TI register size. This field returns 0s when read, indicating that the TI registers require a 16K-byte

region of memory.

 

 

 

 

 

 

 

3

TI_PF

R

TI register prefetch. Bit 3 returns 0 when read, indicating that the TI registers are nonprefetchable.

 

 

 

 

2−1

TI_MEMTYPE

R

TI memory type. This field returns 0s when read, indicating that the TI base address register is 32 bits

wide and mapping can be done anywhere in the 32-bitmemory space.

 

 

 

 

 

 

 

0

TI_MEM

R

TI memory indicator. Bit 0 returns 0 when read, indicating that the TI registers are mapped into system

memory space.

 

 

 

 

 

 

 

7−7

7.10 CardBus CIS Base Address Register

The internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0s when read. See Table 7−9 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

CardBus CIS base address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

 

13

 

12

 

11

10

9

 

8

7

6

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

CardBus CIS base address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

 

RW

 

RW

 

RW

 

RW

R

R

 

R

R

R

R

R

 

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

 

 

0

 

0

0

0

 

0

0

0

0

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

CardBus CIS base address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

18h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−9. CardBus CIS Base Address Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

 

TYPE

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31−11

 

CIS_BASE

 

 

RW

CIS base address. This field specifies the upper 21 bits of the32-bitCIS base address. If

CARDBUS

 

 

 

 

is sampled high on a GRST, then this field is read-only,returning 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10−4

 

 

CIS_SZ

 

 

 

R

CIS address space size. This field returns 0s when read, indicating that the CIS space requires a

 

 

 

 

 

2K-byteregion of memory.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CIS prefetch. Bit 3 returns 0 when read, indicating that the CIS is nonprefetchable. Furthermore, the

3

 

 

CIS_PF

 

 

 

R

CIS is a byte-accessibleaddress space, and either a doubleword or16-bitword access yields

 

 

 

 

 

 

 

 

 

 

indeterminate results.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2−1

 

CIS_MEMTYPE

 

 

R

CIS memory type. This field returns 0s when read, indicating that the CardBus CIS base address

 

 

 

register is 32 bits wide and mapping can be done anywhere in the 32-bitmemory space.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

CIS_MEM

 

 

 

R

CIS memory indicator. Bit 0 returns 0 when read, indicating that the CIS is mapped into system

 

 

 

 

memory space.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7.11 CardBus CIS Pointer Register

The internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0s when read.

Bit

31

30

29

28

27

26

25

 

24

23

 

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

CardBus CIS pointer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

 

R

R

 

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

 

0

0

 

0

0

0

0

0

0

0

Bit

15

 

14

13

12

11

10

9

 

8

7

 

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

CardBus CIS pointer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

R

R

R

 

R

R

 

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

0

0

0

 

0

0

 

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

CardBus CIS pointer

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

28h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7−8

7.12 Subsystem Identification Register

The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 7.25). See Table 7−10 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

Subsystem identification

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

13

12

 

11

10

 

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

Subsystem identification

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RU

 

RU

RU

RU

 

RU

RU

 

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

 

0

0

 

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Subsystem identification

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

2Ch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Update

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7−10. Subsystem Identification Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

 

 

 

 

31−16 ‡

OHCI_SSID

RU

Subsystem device ID. This field indicates the subsystem device ID.

 

 

 

 

15−0 ‡

OHCI_SSVID

RU

Subsystem vendor ID. This field indicates the subsystem vendor ID.

 

 

 

 

These bits are cleared only by the assertion of GRST.

7.13 Power Management Capabilities Pointer Register

The power management capabilities pointer register provides a pointer into the PCI configuration header where the power-managementregister block resides. The PCI7x21/PCI7x11 configuration header doublewords at offsets 44h and 48h provide thepower-managementregisters. This register isread-onlyand returns 44h when read.

Bit

7

6

5

 

4

 

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

Power management capabilities pointer

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

 

R

 

R

 

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

1

0

 

0

 

0

 

1

0

0

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Power management capabilities pointer

 

 

 

 

 

 

Offset:

34h

 

 

 

 

 

 

 

 

 

 

Type:

Read-only

 

 

 

 

 

 

 

 

 

 

Default:

44h

 

 

 

 

 

 

 

 

 

7−9

7.14 Interrupt Line Register

The interrupt line register communicates interrupt line routing information. See Table 7−11

for a complete description

of the register contents.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

7

 

6

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

Interrupt line

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

 

RW

RW

RW

 

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

Default

1

 

1

1

1

 

1

1

1

1

 

 

 

 

 

 

 

 

 

 

 

Register: Interrupt line

Offset: 3Ch

Type: Read/Write

Default: FFh

 

 

 

Table 7−11. Interrupt Line Register Description

BIT

FIELD NAME

TYPE

 

DESCRIPTION

 

 

 

 

 

7−0

INTR_LINE

RW

 

Interrupt line. This field is programmed by the system and indicates to software which interrupt line the

 

PCI7x21/PCI7x11 PCI_INTA is connected to. The default value for this field is 00h.

 

 

 

 

 

 

 

 

 

7.15 Interrupt Pin Register

The value read from this register is function dependent and depends on the values of bits 28, the tie-allbit (TIEALL), and 29, the interrupt tie bit (INTRTIE), in the system control register (PCI offset 80h, see Section 4.29). The INTRTIE bit is compatible with previous TI CardBus controllers, and when set to 1, ties INTB to INTA internally. The TIEALL bit ties INTA, INTB, INTC, and INTD together internally. The internal interrupt connections set by INTRTIE and TIEALL are communicated to host software through this standard register interface. Thisread-onlyregister is described for all PCI7x21/PCI7x11 functions in Table 7−12.

Bit

7

6

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

Interrupt pin

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

 

R

R

R

R

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

 

0

0

1

0

Register: Interrupt pin

Offset: 3Dh

Type: Read-only

Default: 02h

Table 7−12. PCI Interrupt Pin Register—Read-OnlyINTPIN Per Function

INTRTIE BIT

TIEALL BIT

INTPIN

INTPIN

INTPIN

INTPIN

INTPIN

INTPIN

(BIT 29,

(BIT 28,

FUNCTION 0

FUNCTION 1

FUNCTION 2

FUNCTION 3

FUNCTION 4

FUNCTION 5

OFFSET 80h)

OFFSET 80h)

(CARDBUS)

(CARDBUS)

(1394 OHCI)

(FLASH MEDIA)

(SD HOST)

(SMART CARD)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Determined by

Determined by

Determined by

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bits 6−5

0

0

01h (INTA)

02h (INTB)

03h (INTC)

bits (INT_SEL) in

bits (INT_SEL) in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(INT_SEL) in the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the SD host

the Smart Card

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

flash media

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

general control

general control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

general control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

register (see

register (see

1

0

01h (INTA)

01h (INTA)

03h (INTC)

register (see

Section 12.22)

Section 13.22)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Section 11.21)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

1

01h

(INTA)

 

01h

(INTA)

 

01h

(INTA)

 

01h

(INTA)

 

01h

(INTA)

 

01h

(INTA)

 

NOTE: When configuring the PCI7x21/PCI7x11 functions to share PCI interrupts, multifunction terminal MFUNC3 must be configured as IRQSER prior to setting the INTRTIE bit.

7−10