Texas Instruments Dual-Single Socket CardBus and UntraMedia Controller PCI7621, Dual-Single Socket CardBus and UntraMedia Controller PCI7411, Dual-Single Socket CardBus and UntraMedia Controller PCI7421, Dual-Single Socket CardBus and UntraMedia Controller PCI7611 User Manual

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4.31 General Control Register

The general control register provides top level PCI arbitration control. It also provides the ability to disable the 1394 OHCI function and provides control over miscellaneous new functionality. See Table 4−9 for a complete description of the register contents.

Bit

15

 

14

13

 

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

General control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

RW

 

RW

RW

RW

R

R

R

R

RW

RW

RW

R

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

0

0

0

0

0

0

0

0

0

0

1

1

 

Register:

General control

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

86h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0003h

 

 

 

 

 

 

 

 

 

 

 

 

 

4−21

Table 4−9. General Control Register Description

BIT

SIGNAL

TYPE

 

 

FUNCTION

 

 

 

 

 

 

 

Flash media power control pin polarity. This bit controls the polarity of the MC_PWR_CTRL_0 and

15 ‡

FM_PWR_CTRL

RW

MC_PWR_CTRL_1 terminals.

 

_POL

0

= MC_PWR_CTRL_x terminals are active low (default)

 

 

 

 

 

1

= MC_PWR_CTRL_x terminals are active high

 

 

 

 

 

 

 

Smart Card interface select. This bit controls the selection of the dedicated Smart Card interface

 

 

 

used by the controller.

 

 

 

 

0

= EMV interface selected (default)

14 ‡

SC_IF_SEL

RWU

1

= PCI7x10-styleinterface selected

 

 

 

Note: The PCI7x10-styleinterface is only allowed when bits 9−8 (FM_IF_SEL field) are 01. If bits

 

 

 

9−8 contain any other value, then this bit is 0. Care must be taken in the design to ensure that this

 

 

 

bit can be set to 1 at the same time that bits 9−8 are set to 01.

 

 

 

 

 

 

 

When this bit is set, it reduces the query time for UltraMedia card types.

13 ‡

SIM_MODE

RW

0

= Query time is unaffected (default)

 

 

 

1

= Query time is reduced for simulation purposes

 

 

 

 

 

 

 

When this bit is set, bit 0 in the I/O limit registers (PCI offsets 30h and 38h) for both CardBus functions

12 ‡

IO_LIMIT_SEL

RW

is set.

 

0

= Bit 0 in the I/O limit registers is 0 (default)

 

 

 

 

 

 

1

= Bit 0 in the I/O limit registers is 1

 

 

 

 

 

 

 

When this bit is set, bit 0 in the I/O base registers (PCI offsets 2Ch and 34h) for both CardBus functions

11 ‡

IO_BASE_SEL

RW

is set.

 

0

= Bit 0 in the I/O base registers is 0 (default)

 

 

 

 

 

 

1

= Bit 0 in the I/O base registers is 1

 

 

 

 

 

 

 

Power switch select. This bit selects which power switch is implemented in the system.

10 ‡

12V_SW_SEL

RW

0

= A 1.8-Vcapable power switch (TPS2228) is used (default)

 

 

 

1

= A 12-Vcapable power switch (TPS2226) is used

 

 

 

 

 

 

 

Dedicated flash media interface selection. This field controls the mode of the dedicated flash media

 

 

 

interface.

 

9−8 ‡

FM_IF_SEL

RW

00 = Flash media interface configured as SD/MMC socket + MS socket (default)

01 = Flash media interface configured as 2-in-1(SD/MMC, MS) socket

 

 

 

 

 

 

10 = Flash media interface configured as 3-in-1(SD/MMC, MS, SM/XD) socket

 

 

 

11 = Reserved

 

 

 

 

 

7 ‡

DISABLE_SC

RW

When this bit is set, the Smart Card function is completely nonaccessible and nonfunctional.

 

 

 

 

6 ‡

DISABLE_SD

RW

When this bit is set, the SD host controller function is completely nonaccessible and nonfunctional.

 

 

 

 

5 ‡

DISABLE_FM

RW

When this bit is set, the flash media function is completely nonaccessible and nonfunctional.

 

 

 

 

4 ‡

DISABLE_SKTB

RW

When this bit is set, CardBus socket B (function 1) is completely nonaccessible and nonfunctional.

 

 

 

 

3 ‡

DISABLE_OHCI

RW

When this bit is set, the OHCI 1394 controller function is completely nonaccessible and nonfunctional.

 

 

 

 

 

 

 

Dedicated Smart Card power control. This bit determines how power to the dedicated Smart Card

 

DED_SC_PWR_

 

socket is controlled.

 

2 ‡

RW

0

= Controlled through the SC_PWR_CTRL terminal (default)

CTRL

 

 

1

= Controlled through the VPP voltage of socket B of the CardBus power switch (the design

 

 

 

 

 

 

must ensure that this mode can only be set when CardBus socket B is disabled).

 

 

 

 

 

 

 

 

Controls top level PCI arbitration:

 

 

 

 

00 = 1394 OHCI priority

10 = Flash media/SD host priority

1−0 ‡

ARB_CTRL

RW

01 = CardBus priority

11 = Fair round robin

Note: When flash media/SD host priority is selected, there must be a two-levelpriority scheme with the

 

 

 

 

 

 

first level being a round robin between the flash media and SD host functions and the second level being

 

 

 

a round robin between the CardBus and 1394 functions.

 

 

 

 

 

 

These bits are cleared only by the assertion of GRST.

4−22

4.32 General-PurposeEvent Status Register

The general-purposeevent status register contains status bits that are set when general events occur, and can be programmed to generategeneral-purposeevent signaling through GPE. See Table 4−10 for a complete description of the register contents.

Bit

7

 

6

 

5

4

3

 

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

General-purposeevent status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RCU

RCU

R

RCU

RCU

 

RCU

 

RCU

RCU

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

0

0

 

0

 

0

0

 

Register:

General-purposeevent status

 

 

 

 

 

 

 

Offset:

88h

 

 

 

 

 

 

 

 

 

 

Type:

Read/Clear/Update, Read-only

 

 

 

 

 

 

 

Default:

00h

 

 

 

 

 

 

 

 

 

 

 

 

Table 4−10. General-PurposeEvent Status Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SIGNAL

 

TYPE

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

7 ‡

PWR_STS

 

RCU

Power change status. This bit is set when software changes the VCC or VPP power state of either socket.

6 ‡

VPP12_STS

 

RCU

12-VVPP request status. This bit is set when software has changed the requested VPP level to or from 12 V

 

for either socket.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

RSVD

 

R

Reserved. This bit returns 0 when read. A write has no effect.

 

 

 

 

 

 

 

 

 

4 ‡

GP4_STS

 

RCU

GPI4 status. This bit is set on a change in status of the MFUNC5 terminal input level if configured as a

 

general-purposeinput, GPI4.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 ‡

GP3_STS

 

RCU

GPI3 status. This bit is set on a change in status of the MFUNC4 terminal input level if configured as a

 

general-purposeinput, GPI3.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 ‡

GP2_STS

 

RCU

GPI2 status. This bit is set on a change in status of the MFUNC2 terminal input level if configured as a

 

general-purposeinput, GPI2.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 ‡

GP1_STS

 

RCU

GPI1 status. This bit is set on a change in status of the MFUNC1 terminal input level if configured as a

 

general-purposeinput, GPI1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 ‡

GP0_STS

 

RCU

GPI0 status. This bit is set on a change in status of the MFUNC0 terminal input level if configured as a

 

general-purposeinput, GPI0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This bit is cleared only by the assertion of GRST.

4−23

4.33 General-PurposeEvent Enable Register

The general-purposeevent enable register contains bits that are set to enable GPE signals. See Table 4−11 for a complete description of the register contents.

Bit

7

 

6

 

 

5

 

4

 

3

 

 

 

 

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

General-purposeevent enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

 

 

R

RW

 

 

RW

 

RW

 

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

 

0

 

0

 

0

 

 

 

 

0

 

0

0

 

Register:

General-purposeevent enable

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

89h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

Read-only,Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4−11. General-PurposeEvent Enable Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SIGNAL

 

TYPE

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7 ‡

PWR_EN

 

RW

Power change

GPE

enable. When this bit is set,

GPE

is signaled on PWR_STS events.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6 ‡

VPP12_EN

 

RW

12-VVPP

GPE

enable. When this bit is set,

GPE

is signaled on VPP12_STS events.

 

5

RSVD

 

R

Reserved. This bit returns 0 when read. A write has no effect.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 ‡

GP4_EN

 

RW

GPI4

GPE

enable. When this bit is set,

GPE

is signaled on GP4_STS events.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 ‡

GP3_EN

 

RW

GPI3

GPE

enable. When this bit is set,

GPE

is signaled on GP3_STS events.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 ‡

GP2_EN

 

RW

GPI2

GPE

enable. When this bit is set,

GPE

is signaled on GP2_STS events.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 ‡

GP1_EN

 

RW

GPI1

GPE

enable. When this bit is set,

GPE

is signaled on GP1_STS events.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 ‡

GP0_EN

 

RW

GPI0

GPE

enable. When this bit is set,

GPE

is signaled on GP0_STS events.

 

 

This bit is cleared only by the assertion of GRST.

4.34 General-PurposeInput Register

The general-purposeinput register contains the logical value of the data input to the GPI terminals. See Table 4−12 for a complete description of the register contents.

Bit

7

 

6

 

5

 

4

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

General-purposeinput

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

 

R

 

RU

RU

 

RU

RU

RU

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

 

X

X

 

X

X

X

 

Register:

General-purposeinput

 

 

 

 

 

 

 

Offset:

8Ah

 

 

 

 

 

 

 

 

 

 

Type:

Read/Update, Read-only

 

 

 

 

 

 

 

Default:

XXh

 

 

 

 

 

 

 

 

 

 

 

 

Table 4−12. General-PurposeInput Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SIGNAL

 

TYPE

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

7−5

RSVD

 

R

Reserved. These bits return 0s when read. Writes have no effect.

 

 

 

 

 

 

 

 

4

GPI4_DATA

 

RU

GPI4 data input. This bit represents the logical value of the data input from GPI4.

 

 

 

 

 

 

 

3

GPI3_DATA

 

RU

GPI3 data input. This bit represents the logical value of the data input from GPI3.

 

 

 

 

 

 

 

2

GPI2_DATA

 

RU

GPI2 data input. This bit represents the logical value of the data input from GPI2.

 

 

 

 

 

 

 

1

GPI1_DATA

 

RU

GPI1 data input. This bit represents the logical value of the data input from GPI1.

 

 

 

 

 

 

 

0

GPI0_DATA

 

RU

GPI0 data input. This bit represents the logical value of the data input from GPI0.

 

4−24

4.35 General-PurposeOutput Register

The general-purposeoutput register is used to drive the GPO4−GPO0 outputs. See Table 4−13 for a complete description of the register contents.

Bit

7

6

 

5

 

4

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

General-purposeoutput

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

 

R

 

RW

RW

 

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

 

0

 

0

0

 

0

0

0

 

Register:

General-purposeoutput

 

 

 

 

 

 

 

Offset:

8Bh

 

 

 

 

 

 

 

 

 

 

Type:

Read-only,Read/Write

 

 

 

 

 

 

 

Default:

00h

 

 

 

 

 

 

 

 

 

 

 

Table 4−13. General-PurposeOutput Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SIGNAL

TYPE

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

7−5

RSVD

R

Reserved. These bits return 0s when read. Writes have no effect.

 

 

 

 

 

 

 

 

4 ‡

GPO4_DATA

RW

This bit represents the logical value of the data driven to GPO4.

 

 

 

 

 

 

 

 

3 ‡

GPO3_DATA

RW

This bit represents the logical value of the data driven to GPO3.

 

 

 

 

 

 

 

 

2 ‡

GPO2_DATA

RW

This bit represents the logical value of the data driven to GPO2.

 

 

 

 

 

 

 

 

1 ‡

GPO1_DATA

RW

This bit represents the logical value of the data driven to GPO1.

 

 

 

 

 

 

 

 

0 ‡

GPO0_DATA

RW

This bit represents the logical value of the data driven to GPO0.

 

 

This bit is cleared only by the assertion of GRST.

4−25

4.36 Multifunction Routing Status Register

The multifunction routing status register is used to configure the MFUNC6−MFUNC0 terminals. These terminals may be configured for various functions. This register is intended to be programmed once at power-oninitialization. The default value for this register can also be loaded through a serial EEPROM. See Table 4−14 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

Multifunction routing status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

RW

RW

RW

R

RW

RW

RW

R

RW

RW

RW

R

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

 

 

13

 

 

12

 

11

 

 

 

10

9

8

7

6

 

5

4

 

3

 

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Multifunction routing status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

RW

 

RW

 

RW

 

 

R

 

 

 

RW

RW

RW

R

RW

 

RW

RW

 

R

 

RW

 

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

 

0

 

 

1

 

0

 

 

 

0

0

0

0

0

 

0

0

 

0

 

0

 

0

0

 

Register:

 

Multifunction routing status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

 

 

8Ch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

 

 

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0000 1000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4−14. Multifunction Routing Status Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SIGNAL

 

TYPE

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31−28 ‡

RSVD

 

 

 

R

Bits 31−28 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal

 

 

 

 

 

 

 

 

as follows:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27−24 ‡

MFUNC6

 

RW

 

0000

= RSVD

 

0100 = IRQ4

1000 = IRQ8

 

1100 = IRQ12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0001

= CLKRUN

0101 = IRQ5

1001 = IRQ9

 

1101 = IRQ13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0010

= IRQ2

 

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0011 = IRQ3

 

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal

 

 

 

 

 

 

 

 

as follows:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23−20 ‡

MFUNC5

 

RW

 

0000

= GPI4

 

0100 = SC_DBG_RX

1000 = CAUDPWM

1100 = LEDA1

 

 

 

 

0001

= GPO4

 

0101 = IRQ5

 

1001 = IRQ9

 

 

1101 = LED_SKT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0010

=

PCGNT

 

 

 

0110 = RSVD

 

1010 = FM_LED

1110 = GPE

 

 

 

 

 

 

 

 

 

 

 

0011 = IRQ3

 

0111 = RSVD

 

1011 = OHCI_LED

1111 = IRQ15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal

 

 

 

 

 

 

 

 

as follows:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19−16 ‡

MFUNC4

 

RW

 

0000

= GPI3

 

0100 = IRQ4

 

1000 = CAUDPWM

1100 =

RI_OUT

 

 

 

 

0001

= GPO3

 

0101 = SC_DBG_TX

1001 = IRQ9

 

 

1101 = LED_SKT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0010

= RSVD

 

0110 = RSVD

 

1010 = INTD

 

 

1110 = GPE

 

 

 

 

 

 

 

 

 

 

 

0011 = IRQ3

 

0111 = RSVD

 

1011 = FM_LED

1111 = IRQ15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal

 

 

 

 

 

 

 

 

as follows:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15−12 ‡

MFUNC3

 

RW

 

0000

= RSVD

 

0100 = IRQ4

1000 = IRQ8

 

1100 = IRQ12

 

 

 

 

 

 

 

0001

= IRQSER

 

0101 = IRQ5

1001 = IRQ9

 

1101 = IRQ13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0010

= IRQ2

 

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0011 = IRQ3

 

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal

 

 

 

 

 

 

 

 

as follows:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11−8 ‡

MFUNC2

 

RW

 

0000

= GPI2

 

0100 = IRQ4

1000 = CAUDPWM

1100 =

RI_OUT

 

 

 

 

 

0001

= GPO2

 

0101 = IRQ5

1001 = FM_LED

1101 = TEST_MUX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0010

=

PCREQ

 

 

0110 = RSVD

1010 = IRQ10

1110 = GPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0011 = IRQ3

 

0111 = RSVD

1011 = INTC

 

1111 = IRQ7

 

 

 

 

 

These bits are cleared only by the assertion of GRST.

4−26

Table 4−14. Multifunction Routing Status Register Description (Continued)

BIT

SIGNAL

TYPE

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal

 

 

 

as follows:

 

 

 

 

 

7−4 ‡

MFUNC1

RW

0000

= GPI1

0100

= OHCI_LED 1000

= CAUDPWM

1100 = LEDA1

0001

= GPO1

0101

= IRQ5

1001

= IRQ9

1101 = LEDA2

 

 

 

 

 

 

0010

= INTB

0110 = RSVD

1010

= IRQ10

1110 = GPE

 

 

 

0011 = IRQ3

0111 = RSVD

1011 = IRQ11

1111 = IRQ15

 

 

 

 

 

 

 

Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal

 

 

 

as follows:

 

 

 

 

 

3−0 ‡

MFUNC0

RW

0000

= GPI0

0100

= IRQ4

1000

= CAUDPWM

1100 = LEDA1

0001

= GPO0

0101

= IRQ5

1001

= IRQ9

1101 = LEDA2

 

 

 

 

 

 

0010

= INTA

0110 = RSVD

1010

= IRQ10

1110 = GPE

 

 

 

0011 = IRQ3

0111 = RSVD

1011 = IRQ11

1111 = IRQ15

These bits are cleared only by the assertion of GRST.

4.37 Retry Status Register

The contents of the retry status register enable the retry time-outcounters and display the retry expiration status. The flags are set when the PCI7x21/PCI7x11 controller, as a master, receives a retry and does not retry the request within 215 clock cycles. The flags are cleared by writing a 1 to the bit. Access this register only through function 0. See Table 4−15 for a complete description of the register contents.

Bit

7

 

6

 

 

 

5

 

4

 

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

Retry status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

 

 

RC

 

R

 

RC

 

R

RC

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

1

 

1

 

 

 

0

 

0

 

0

 

0

0

0

 

Register:

Retry status

 

 

 

 

 

 

 

 

Offset:

90h (Functions 0, 1)

 

 

 

 

 

 

 

 

Type:

Read-only,Read/Write, Read/Clear

 

 

 

 

 

 

Default:

C0h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4−15. Retry Status Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SIGNAL

 

TYPE

 

 

 

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI retry time-outcounter enable. This bit is encoded as:

 

 

 

7 ‡

PCIRETRY

 

RW

 

0

= PCI retry counter disabled

 

 

 

 

 

 

 

 

 

 

1

= PCI retry counter enabled (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus retry time-outcounter enable. This bit is encoded as:

 

 

 

6 ‡§

CBRETRY

 

RW

 

0

= CardBus retry counter disabled

 

 

 

 

 

 

 

 

 

 

1

= CardBus retry counter enabled (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus target B retry expired. Write a 1 to clear this bit.

 

 

 

5 ‡

TEXP_CBB

 

RC

 

0

= Inactive (default)

 

 

 

 

 

 

 

 

 

 

 

 

1

= Retry has expired.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

RSVD

 

R

 

Reserved. This bit returns 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus target A retry expired. Write a 1 to clear this bit.

 

 

 

3 ‡§

TEXP_CBA

 

RC

 

0

= Inactive (default)

 

 

 

 

 

 

 

 

 

 

 

 

1

= Retry has expired.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

RSVD

 

R

 

Reserved. This bit returns 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI target retry expired. Write a 1 to clear this bit.

 

 

 

1 ‡

TEXP_PCI

 

RC

 

0

= Inactive (default)

 

 

 

 

 

 

 

 

 

 

 

 

1

= Retry has expired.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

RSVD

 

R

 

Reserved. This bit returns 0 when read.

 

 

 

 

 

This bit is cleared only by the assertion of GRST.

§ These bits are global in nature and must be accessed only through function 0.

4−27

4.38 Card Control Register

The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register, and the enable bit is shared between functions 0 and 1. See Table 4−16 for a complete description of the register contents.

The RI_OUT signal is enabled through this register, and the enable bit is shared between functions 0 and 1.

Bit

7

6

 

5

 

 

4

 

 

3

 

 

2

 

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

Card control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

 

 

RW

 

R

 

 

R

 

RW

 

RW

 

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

 

0

 

 

0

 

 

0

 

 

0

 

0

 

0

 

Register:

Card control

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

91h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

Read-only,Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

Default:

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4−16. Card Control Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SIGNAL

TYPE

 

 

 

 

 

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7 ‡§

RIENB

RW

Ring indicate enable. When this bit is 1, the

RI_OUT

output is enabled. This bit defaults to 0.

 

 

 

 

 

 

 

 

 

 

 

6−3

RSVD

RW

These bits are reserved. Do not change the value of these bits.

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus audio-to-MFUNC.When this bit is set, the CAUDIO CardBus signal must be routed through an

2 ‡

AUD2MUX

RW

MFUNC terminal. If this bit is set for both functions, then function 0 is routed.

 

 

 

0

= CAUDIO set to CAUDPWM on MFUNC terminal (default)

 

 

 

 

 

 

 

 

 

 

 

 

1

= CAUDIO is not routed.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When bit 1 is set, the

SPKR

terminal from the PC Card is enabled and is routed to tthe SPKROUT terminal.

 

 

 

The SPKR signal from socket 0 is XORed with the SPKR signal from socket 1 and sent to SPKROUT. The

1 ‡

SPKROUTEN

RW

SPKROUT terminal drives data only when the SPKROUTEN bit of either function is set. This bit is encoded

as:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

=

SPKR

to SPKROUT not enabled (default)

 

 

 

 

 

 

 

 

1

= SPKR to SPKROUT enabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt flag. This bit is the interrupt flag for 16-bitI/O PC Cards and for CardBus cards. This bit is set when

 

 

 

a functional interrupt is signaled from a PC Card interface, and is socket dependent (i.e., not global). Write

0 ‡

IFG

RW

back a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

= No PC Card functional interrupt detected (default)

 

 

 

 

 

 

 

 

1

= PC Card functional interrupt detected

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This bit is cleared only by the assertion of GRST.

§ This bit is global in nature and must be accessed only through function 0.

4−28

4.39 Device Control Register

The device control register is provided for PCI1130 compatibility. It contains bits that are shared between functions 0 and 1. The interrupt mode select is programmed through this register. The socket-capableforce bits are also programmed through this register. See Table 4−17 for a complete description of the register contents.

Bit

7

6

 

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

Device control

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

 

RW

R

 

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

Default

0

1

 

1

0

 

0

1

1

0

 

Register:

Device control

 

 

 

 

 

 

 

 

Offset:

92h (Functions 0, 1)

 

 

 

 

 

 

 

Type:

Read-only,Read/Write

 

 

 

 

 

 

 

Default:

66h

 

 

 

 

 

 

 

Table 4−17. Device Control Register Description

BIT

SIGNAL

TYPE

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Socket power lock bit. When this bit is set to 1, software cannot power down the PC Card socket while

7 ‡

SKTPWR_LOCK

RW

in D3. It may be necessary to lock socket power in order to support wake on LAN or RING if the

operating system is programmed to power down a socket when the CardBus controller is placed in the

 

 

 

 

 

 

D3 state.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3-Vsocket capable force bit.

6 ‡§

3VCAPABLE

RW

0 = Not 3-Vcapable

 

 

 

1 = 3-Vcapable (default)

 

 

 

 

 

 

 

 

 

 

 

 

5 ‡

IO16R2

RW

Diagnostic bit. This bit defaults to 1.

 

 

 

 

 

 

 

 

 

 

 

 

4

RSVD

R

Reserved. This bit returns 0 when read. A write has no effect.

 

 

 

 

 

 

 

 

 

 

 

 

3 ‡§

TEST

RW

TI test bit. Write only 0 to this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded:

 

 

 

00 = Parallel PCI interrupts only

2−1 ‡§

INTMODE

RW

01 = Reserved

 

 

 

10 = IRQ serialized interrupts and parallel PCI interrupts

INTA,

 

INTB,

 

INTC,

and

INTD

 

 

 

 

11 = IRQ and PCI serialized interrupts (default)

 

 

 

 

0 ‡§

RSVD

RW

Reserved. Bit 0 is reserved for test purposes. Only a 0 must be written to this bit.

This bit is cleared only by the assertion of GRST.

§ These bits are global in nature and must be accessed only through function 0.

4−29

4.40 Diagnostic Register

The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s must be written to it. See Table 4−18 for a complete description of the register contents.

Bit

7

6

 

5

4

 

3

 

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

Diagnostic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

R

 

RW

RW

 

RW

 

RW

 

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

1

 

1

0

 

0

 

0

 

0

0

 

 

Register:

Diagnostic

 

 

 

 

 

 

 

 

 

 

Offset:

93h (functions 0, 1)

 

 

 

 

 

 

 

 

 

 

Type:

Read/Write

 

 

 

 

 

 

 

 

 

 

Default:

60h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4−18. Diagnostic Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

SIGNAL

TYPE

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This bit defaults to 0. This bit is encoded as:

 

 

 

 

7 ‡§

 

TRUE_VAL

RW

0 = Reads true values in PCI vendor ID and PCI device ID registers (default)

 

 

 

 

 

1 = Returns all 1s to reads from the PCI vendor ID and PCI device ID registers

 

 

 

 

 

 

 

 

 

 

6 ‡

 

RSVD

R

Reserved. This bit is read-onlyand returns 1 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CSC interrupt routing control

 

 

 

 

 

 

 

5 ‡

 

CSC

RW

0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1

 

 

 

 

 

1 = CSC interrupts routed to PCI if ExCA 805 bits 7−4 = 0000b (default).

 

 

 

 

 

 

 

 

 

 

 

 

 

In this case, the setting of ExCA 803 bit 4 is a don’t care.

 

 

 

 

 

 

 

 

 

 

 

4 ‡§

 

DIAG4

RW

Diagnostic RETRY_DIS. Delayed transaction disable.

 

 

 

 

 

 

 

 

 

 

 

3 ‡§

 

DIAG3

RW

Diagnostic RETRY_EXT. Extends the latency from 16 to 64.

 

 

 

 

 

 

 

 

 

2 ‡§

 

DIAG2

RW

Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215.

 

 

1 ‡§

 

DIAG1

RW

Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215.

 

 

0 ‡

 

RSVD

RW

These bits are reserved. Do not change the value of these bits.

 

 

This bit is cleared only by the assertion of GRST.

§ This bit is global and is accessed only through function 0.

4−30