Texas Instruments Dual-Single Socket CardBus and UntraMedia Controller PCI7621, Dual-Single Socket CardBus and UntraMedia Controller PCI7411, Dual-Single Socket CardBus and UntraMedia Controller PCI7421, Dual-Single Socket CardBus and UntraMedia Controller PCI7611 User Manual

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4 PC Card Controller Programming Model

This chapter describes the PCI7x21/PCI7x11 PCI configuration registers that make up the 256-bytePCI configuration header for each PCI7x21/PCI7x11 function. There are some bits which affect both CardBus functions, but which, in order to work properly, must be accessed only through function 0. These are called global bits. Registers containing one or more global bits are denoted by § in Table 4−2.

Any bit followed by a † is not cleared by the assertion of PRST (see CardBus Bridge Power Management, Section 3.8.10, for more details) if PME is enabled (PCI offset A4h, bit 8). In this case, these bits are cleared only by GRST. If PME is not enabled, then these bits are cleared by GRST or PRST. These bits are sometimes referred to as PME context bits and are implemented to allow PME context to be preserved during the transition from D3hot or D3cold to D0.

If a bit is followed by a ‡, then this bit is cleared only by GRST in all cases (not conditional on PME being enabled). These bits are intended to maintain device context such as interrupt routing and MFUNC programming during warm resets.

A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1 describes the field access tags.

Table 4−1. Bit Field Access Tag Descriptions

ACCESS TAG

NAME

MEANING

 

 

 

R

Read

Field can be read by software.

 

 

 

W

Write

Field can be written by software to any value.

 

 

 

S

Set

Field can be set by a write of 1. Writes of 0 have no effect.

 

 

 

C

Clear

Field can be cleared by a write of 1. Writes of 0 have no effect.

 

 

 

U

Update

Field can be autonomously updated by the PCI7x21/PCI7x11 controller.

 

 

 

4.1 PCI Configuration Register Map (Functions 0 and 1)

The PCI7x21/PCI7x11 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1. The configuration header, compliant with the PCI Local Bus Specification as a CardBus bridge header, isPC99/PC2001 compliant as well. Table 4−2 illustrates the PCI configuration register map, which includes both the predefined portion of the configuration space and theuser-definableregisters.

Table 4−2. Functions 0 and 1 PCI Configuration Register Map

 

 

REGISTER NAME

 

OFFSET

 

 

 

 

 

 

Device ID

Vendor ID

 

00h

 

 

 

 

 

 

 

 

Status ‡

Command

 

04h

 

 

 

 

 

 

 

 

 

Class code

 

 

Revision ID

08h

 

 

 

 

 

 

 

BIST

 

Header type

Latency timer

 

Cache line size

0Ch

 

 

 

 

 

 

 

 

 

CardBus socket registers/ExCA base address register

 

10h

 

 

 

 

Secondary status ‡

Reserved

 

Capability pointer

14h

 

 

 

 

 

 

 

CardBus latency timer

 

Subordinate bus number

CardBus bus number

 

PCI bus number

18h

 

 

 

 

 

 

 

 

 

CardBus memory base register 0

 

1Ch

 

 

 

 

 

 

 

CardBus memory limit register 0

 

20h

 

 

 

 

 

 

 

CardBus memory base register 1

 

24h

 

 

 

 

 

 

 

CardBus memory limit register 1

 

28h

One or more bits in this register are cleared only by the assertion of GRST.

4−1

Table 4−2. Functions 0 and 1 PCI Configuration Register Map (Continued)

 

REGISTER NAME

 

OFFSET

 

 

 

 

 

 

CardBus I/O base register 0

 

2Ch

 

 

 

 

 

 

CardBus I/O limit register 0

 

30h

 

 

 

 

 

 

CardBus I/O base register 1

 

34h

 

 

 

 

 

 

CardBus I/O limit register 1

 

38h

 

 

 

 

 

Bridge control †

 

Interrupt pin

Interrupt line

3Ch

 

 

 

 

 

 

Subsystem ID ‡

 

Subsystem vendor ID ‡

40h

 

 

 

 

 

 

PC Card 16-bitI/Flegacy-modebase-address

 

44h

 

 

 

 

 

 

Reserved

 

 

48h−7Ch

 

 

 

 

 

System control †‡§

 

80h

 

 

 

 

 

General control ‡§

 

Reserved

MC_CD debounce ‡

84h

 

 

 

 

 

 

General-purposeoutput ‡

General-purposeinput

 

General-purposeevent

General-purposeevent

88h

 

enable ‡

status ‡

 

 

 

 

 

 

 

 

 

 

Multifunction routing status ‡

 

8Ch

 

 

 

 

 

Diagnostic ‡§

Device control ‡§

 

Card control ‡§

Retry status ‡§

90h

 

 

 

 

 

 

 

Reserved

 

 

94h−9Ch

 

 

 

 

Power management capabilities ‡

 

Next item pointer

Capability ID

A0h

 

 

 

 

 

 

Power management data

Power management

 

 

 

 

control/status bridge support

 

Power management control/status †‡

A4h

(Reserved)

 

extensions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

A8h−ACh

 

 

 

 

 

Serial bus control/status ‡

Serial bus slave address ‡

 

Serial bus index ‡

Serial bus data ‡

B0h

 

 

 

 

 

 

 

Reserved

 

 

B4h−FCh

 

 

 

 

 

 

One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST.

One or more bits in this register are cleared only by the assertion of GRST.

§ One or more bits in this register are global in nature and must be accessed only through function 0.

4.2 Vendor ID Register

The vendor ID register contains a value allocated by the PCI SIG that identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch.

Bit

15

 

14

13

 

12

11

 

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

Vendor ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

 

R

R

 

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

1

0

 

0

0

0

0

1

0

0

1

1

0

0

 

Register:

Vendor ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

00h (Functions 0, 1)

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

104Ch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4−2

4.3 Device ID Register Functions 0 and 1

This read-onlyregister contains the device ID assigned by TI to the PCI7x21/PCI7x11 CardBus controller functions (PCI functions 0 and 1).

Bit

15

 

14

13

 

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

Device ID—SmartCard enabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

 

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

1

 

0

0

 

0

0

0

0

0

0

0

1

1

0

0

0

1

 

Register:

Device ID

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

02h (Functions 0 and 1)

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

8031h

 

 

 

 

 

 

 

 

 

 

 

 

 

4−3

4.4 Command Register

The PCI command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification (see Table 4−3). None of the bit functions in this register are shared among the PCI7x21/PCI7x11 PCI functions. Three command registers exist in the PCI7x21/PCI7x11 controller, one for each function. Software manipulates the PCI7x21/PCI7x11 functions as separate entities when enabling functionality through the command register. The SERR_EN and PERR_EN enable bits in this register are internally wired OR between the three functions, and these control bits appear to software to be separate for each function.

Bit

15

 

14

13

 

12

 

11

 

10

 

 

9

 

8

 

7

 

6

 

5

4

 

 

3

2

 

 

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Command

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

 

 

R

R

 

RW

 

R

RW

 

R

 

RW

 

RW

R

 

R

RW

 

RW

 

 

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

 

0

 

0

 

 

0

 

0

 

0

 

0

 

0

0

 

 

0

0

 

 

0

 

0

 

 

 

Register:

Command

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

04h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only,Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4−3. Command Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

SIGNAL

TYPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15−11

 

RSVD

 

R

Reserved. Bits 15−11 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTx

disable. When set to 1, this bit disables the function from asserting interrupts on the

INTx

signals.

10

 

INT_DISABLE

RW

 

0 = INTx assertion is enabled (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 = INTx assertion is disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

FBB_EN

R

Fast

back-to-back

enable. The

PCI7x21/PCI7x11

controller

does not

generate

fast

back-to-back

 

transactions; therefore, this bit is read-only.This bit returns a 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System error

(SERR)

enable. This bit controls the enable for the

SERR

driver on the PCI interface.

SERR

 

 

 

 

 

 

 

 

can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set

8

 

SERR_EN

RW

for the PCI7x21/PCI7x11 controller to report address parity errors.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = Disables the SERR output driver (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 = Enables the SERR output driver

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

RSVD

 

R

Reserved. Bit 7 returns 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parity error response enable. This bit controls the PCI7x21/PCI7x11 response to parity errors through the

 

 

 

 

 

 

 

PERR signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated

6

 

PERR_EN

RW

by asserting

SERR.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = PCI7x21/PCI7x11 controller ignores detected parity errors (default).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 = PCI7x21/PCI7x11 controller responds to detected parity errors.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI7x21/PCI7x11 controller does

5

 

VGA_EN

RW

not respond to palette register writes and snoops the data). When the bit is 0, the PCI7x21/PCI7x11

 

 

 

 

 

 

 

controller treats all palette accesses like all other accesses.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory write-and-invalidateenable. This bit controls whether a PCI initiator device can generate memory

4

 

MWI_EN

R

write-and-invalidate

commands.

The

PCI7x21/PCI7x11 controller does

not

support

memory

 

write-and-invalidatecommands, it uses memory write commands instead; therefore, this bit is hardwired

 

 

 

 

 

 

 

 

 

 

 

 

 

 

to 0. This bit returns 0 when read. Writes to this bit have no effect.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The

3

 

SPECIAL

R

PCI7x21/PCI7x11 controller does not respond to special cycle operations; therefore, this bit is hardwired

 

 

 

 

 

 

 

to 0. This bit returns 0 when read. Writes to this bit have no effect.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bus master control. This bit controls whether or not the PCI7x21/PCI7x11 controller can act as a PCI bus

2

 

MAST_EN

RW

initiator (master). The PCI7x21/PCI7x11 controller can take control of the PCI bus only when this bit is set.

 

 

0 = Disables the PCI7x21/PCI7x11 ability to generate PCI bus accesses (default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 = Enables the PCI7x21/PCI7x11 ability to generate PCI bus accesses

 

 

 

 

 

 

 

 

4−4

Table 4−3. Command Register Description (continued)

BIT

SIGNAL

TYPE

 

FUNCTION

 

 

 

 

 

 

 

Memory space enable. This bit controls whether or not the PCI7x21/PCI7x11 controller can claim cycles

1

MEM_EN

RW

in PCI memory space.

0

= Disables the PCI7x21/PCI7x11 response to memory space accesses (default)

 

 

 

 

 

 

1

= Enables the PCI7x21/PCI7x11 response to memory space accesses

 

 

 

 

 

 

 

I/O space control. This bit controls whether or not the PCI7x21/PCI7x11 controller can claim cycles in PCI

0

IO_EN

RW

I/O space.

0

= Disables the PCI7x21/PCI7x11 controller from responding to I/O space accesses (default)

 

 

 

 

 

 

1

= Enables the PCI7x21/PCI7x11 controller to respond to I/O space accesses

4.5 Status Register

The status register provides device information to the host system. Bits in this register can be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. PCI bus status is shown through each function. See Table 4−4 for a complete description of the register contents.

Bit

15

 

14

 

13

12

 

11

 

10

 

9

8

 

 

7

 

6

 

 

5

4

 

3

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

 

RW

RW

RW

 

RW

 

R

 

R

RW

 

 

R

 

 

 

R

 

 

R

R

 

RU

R

 

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

0

 

0

 

0

 

1

0

 

 

0

 

0

 

 

0

1

 

0

0

 

0

0

 

 

Register:

Status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

 

06h (Functions 0, 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

 

Read-only,Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0210h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4−4. Status Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

SIGNAL

 

TYPE

 

 

 

 

 

 

 

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15 ‡

 

PAR_ERR

 

RW

Detected parity error. This bit is set when a parity error is detected, either an address or data parity error.

 

 

Write a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14 ‡

 

SYS_ERR

 

RW

Signaled system error. This bit is set when

SERR

is enabled and the PCI7x21/PCI7x11 controller signaled

 

 

a system error to the host. Write a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13 ‡

 

MABORT

 

RW

Received master abort. This bit is set when a cycle initiated by the PCI7x21/PCI7x11 controller on the PCI

 

 

bus has been terminated by a master abort. Write a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12 ‡

 

TABT_REC

 

RW

Received target abort. This bit is set when a cycle initiated by the PCI7x21/PCI7x11 controller on the PCI

 

 

bus was terminated by a target abort. Write a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11 ‡

 

TABT_SIG

 

RW

Signaled target abort. This bit is set by the PCI7x21/PCI7x11 controller when it terminates a transaction on

 

 

the PCI bus with a target abort. Write a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10−9

 

PCI_SPEED

 

R

DEVSEL timing. These bits encode the timing of

DEVSEL

and are hardwired to 01b indicating that the

 

 

PCI7x21/PCI7x11 controller asserts this signal at a medium speed on nonconfiguration cycle accesses.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data parity error detected. Write a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = The conditions for setting this bit have not been met.

 

 

 

 

 

 

 

 

8 ‡

 

DATAPAR

 

RW

1 = A data parity error occurred and the following conditions were met:

 

 

 

 

 

 

 

 

a. PERR was asserted by any PCI device including the PCI7x21/PCI7x11 controller.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b. The PCI7x21/PCI7x11 controller was the bus master during the data parity error.

 

 

 

 

 

 

 

 

 

 

c. The parity error response bit is set in the command register.

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

FBB_CAP

 

R

Fast back-to-backcapable. The PCI7x21/PCI7x11 controller cannot accept fastback-to-backtransactions;

 

 

thus, this bit is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

UDF

 

 

R

UDF supported. The PCI7x21/PCI7x11 controller does not support user-definablefeatures; therefore, this

 

 

 

bit is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

66MHZ

 

R

66-MHzcapable. The PCI7x21/PCI7x11 controller operates at a maximum PCLK frequency of 33 MHz;

 

 

therefore, this bit is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This bit is cleared only by the assertion of GRST.

4−5

 

 

 

Table 4−4. Status Register Description (continued)

 

 

 

 

BIT

SIGNAL

TYPE

FUNCTION

 

 

 

 

 

 

 

Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI

4

CAPLIST

R

capabilities are implemented. The linked list of PCI power-managementcapabilities is implemented in this

 

 

 

function.

 

 

 

 

 

 

 

Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the

3

INT_STATUS

RU

command register (PCI offset 04h, see Section 4.4) is a 0 and this bit is a 1, is the function’s INTx signal

 

 

 

asserted. Setting the INT_DISABLE bit to a 1 has no effect on the state of this bit.

 

 

 

 

2−0

RSVD

R

Reserved. These bits return 0s when read.

 

 

 

 

4.6 Revision ID Register

The revision ID register indicates the silicon revision of the PCI7x21/PCI7x11 controller.

Bit

7

6

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

Revision ID

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

 

R

R

R

R

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

 

0

0

0

0

 

Register:

Revision ID

 

 

 

 

 

 

 

 

Offset:

08h (functions 0, 1)

 

 

 

 

 

 

 

Type:

Read-only

 

 

 

 

 

 

 

 

Default:

00h

 

 

 

 

 

 

 

4.7 Class Code Register

The class code register recognizes PCI7x21/PCI7x11 functions 0 and 1 as a bridge device (06h) and a CardBus bridge device (07h), with a 00h programming interface.

Bit

23

22

 

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

 

5

4

3

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

PCI class code

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Base class

 

 

 

 

 

 

Subclass

 

 

 

 

 

Programming interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

 

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

R

R

R

R

 

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

 

0

0

0

1

1

0

0

0

0

0

0

1

1

1

0

0

 

0

0

0

0

 

0

0

 

Register:

 

PCI class code

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

09h (functions 0, 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

06 0700h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.8 Cache Line Size Register

The cache line size register is programmed by host software to indicate the system cache line size.

Bit

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

Name

 

 

 

Cache line size

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

Register: Cache line size

Offset: 0Ch (Functions 0, 1)

Type: Read/Write

Default: 00h

4−6

4.9 Latency Timer Register

The latency timer register specifies the latency timer for the PCI7x21/PCI7x11 controller, in units of PCI clock cycles. When the PCI7x21/PCI7x11 controller is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCI7x21/PCI7x11 transaction has terminated, then the PCI7x21/PCI7x11 controller terminates the transaction when its GNT is deasserted.

Bit

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

Name

 

 

 

Latency timer

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

Register: Latency timer

Offset: 0Dh

Type: Read/Write

Default: 00h

4.10 Header Type Register

The header type register returns 82h when read, indicating that the PCI7x21/PCI7x11 functions 0 and 1 configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI registers 00h−7Fh, and 80h−FFh is user-definableextension registers.

Bit

7

6

 

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

Header type

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

 

R

R

 

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

Default

1

0

 

0

0

 

0

0

1

0

 

Register:

Header type

 

 

 

 

 

 

 

 

Offset:

0Eh (Functions 0, 1)

 

 

 

 

 

 

 

Type:

Read-only

 

 

 

 

 

 

 

 

Default:

82h

 

 

 

 

 

 

 

4.11 BIST Register

Because the PCI7x21/PCI7x11 controller does not support a built-inself-test(BIST), this register returns the value of 00h when read.

Bit

7

6

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

BIST

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

 

R

R

R

R

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

 

0

0

0

0

 

Register:

BIST

 

 

 

 

 

 

 

 

Offset:

0Fh (Functions 0, 1)

 

 

 

 

 

 

 

Type:

Read-only

 

 

 

 

 

 

 

 

Default:

00h

 

 

 

 

 

 

 

4−7

4.12 CardBus Socket Registers/ExCA Base Address Register

This register is programmed with a base address referencing the CardBus socket registers and the memory-mappedExCA register set. Bits 31−12 are read/write, and allow the base address to be located anywhere in the32-bitPCI memory address space on a4-Kbyteboundary. Bits 11−0 areread-only,returning 0s when read. When software writes all 1s to this register, the value read back is FFFF F000h, indicating that at least 4K bytes of memory address space are required. The CardBus registers start at offset 000h, and thememory-mappedExCA registers begin at offset 800h. This register is not shared by functions 0 and 1, so the system maps each socket control register separately.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

CardBus socket registers/ExCA base address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

 

 

 

 

 

 

CardBus socket registers/ExCA base address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

 

RW

RW

RW

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

Register:

CardBus socket registers/ExCA base address

 

 

 

 

 

 

 

Offset:

 

10h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only,Read/Write

 

 

 

 

 

 

 

 

 

 

 

Default:

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

4.13 Capability Pointer Register

The capability pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each socket has its own capability pointer register. This register is read-onlyand returns A0h when read.

Bit

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

Name

 

 

 

Capability pointer

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

Default

1

0

1

0

0

0

0

0

Register: Capability pointer

Offset: 14h

Type: Read-only

Default: A0h

4−8

4.14 Secondary Status Register

The secondary status register is compatible with the PCI-PCIbridge secondary status register. It indicatesCardBus-relateddevice information to the host system. This register is very similar to the PCI status register (PCI offset 06h, see Section 4.5), and status bits are cleared by a writing a 1. This register is not shared by the two socket functions, but is accessed on aper-socketbasis. See Table 4−5 for a complete description of the register contents.

Bit

15

 

14

13

 

12

11

10

 

9

 

8

 

 

7

 

 

6

 

5

 

4

 

3

 

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

Secondary status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RC

 

RC

RC

 

RC

RC

R

 

R

RC

 

 

R

 

 

R

 

R

 

R

 

R

 

R

 

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

0

0

 

1

 

0

 

 

0

 

 

0

 

0

 

0

 

0

 

0

 

0

0

 

Register:

Secondary status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

16h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only,Read/Clear

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0200h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4−5. Secondary Status Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SIGNAL

TYPE

 

 

 

 

 

 

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15 ‡

CBPARITY

RC

Detected parity error. This bit is set when a CardBus parity error is detected, either an address or data

parity error. Write a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14 ‡

CBSERR

RC

Signaled system error. This bit is set when

CSERR

is signaled by a CardBus card. The PCI7x21/PCI7x11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

controller does not assert the CSERR signal. Write a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13 ‡

CBMABORT

RC

Received master abort. This bit is set when a cycle initiated by the PCI7x21/PCI7x11 controller on the

CardBus bus is terminated by a master abort. Write a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12 ‡

REC_CBTA

RC

Received target abort. This bit is set when a cycle initiated by the PCI7x21/PCI7x11 controller on the

CardBus bus is terminated by a target abort. Write a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11 ‡

SIG_CBTA

RC

Signaled target abort. This bit is set by the PCI7x21/PCI7x11 controller when it terminates a transaction

on the CardBus bus with a target abort. Write a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10−9

CB_SPEED

R

CDEVSEL timing. These bits encode the timing of

CDEVSEL

and are hardwired to 01b indicating that the

PCI7x21/PCI7x11 controller asserts this signal at a medium speed.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CardBus data parity error detected. Write a 1 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = The conditions for setting this bit have not been met.

 

 

 

 

 

 

 

 

8 ‡

CB_DPAR

RC

1 = A data parity error occurred and the following conditions were met:

 

 

 

 

 

 

 

a. CPERR was asserted on the CardBus interface.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b. The PCI7x21/PCI7x11 controller was the bus master during the data parity error.

 

 

 

 

 

 

 

 

c. The parity error response enable bit (bit 0) is set in the bridge control register (PCI offset 3Eh,

 

 

 

 

 

 

 

see Section 4.25).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

CBFBB_CAP

R

Fast

back-to-backcapable.

The PCI7x21/PCI7x11 controller

cannot

accept

fast

back-to-back

transactions; therefore, this bit is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

CB_UDF

R

User-definable

feature

support. The

PCI7x21/PCI7x11

controller does

not support

user-definable

features; therefore, this bit is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

CB66MHZ

R

66-MHzcapable. The PCI7x21/PCI7x11 CardBus interface operates at a maximum CCLK frequency of

33 MHz; therefore, this bit is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4−0

RSVD

R

These bits return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This bit is cleared only by the assertion of GRST.

4−9

4.15 PCI Bus Number Register

The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI7x21/PCI7x11 controller is connected. The PCI7x21/PCI7x11 controller uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses.

Bit

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

Name

 

 

 

PCI bus number

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

Register: PCI bus number

Offset: 18h (Functions 0, 1)

Type: Read/Write

Default: 00h

4.16 CardBus Bus Number Register

The CardBus bus number register is programmed by the host system to indicate the bus number of the CardBus bus to which the PCI7x21/PCI7x11 controller is connected. The PCI7x21/PCI7x11 controller uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each PCI7x21/PCI7x11 controller function.

Bit

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

Name

 

 

 

CardBus bus number

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

RW

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

 

Register:

CardBus bus number

 

 

 

 

 

 

Offset:

19h

 

 

 

 

 

 

 

Type:

Read/Write

 

 

 

 

 

 

 

Default:

00h

 

 

 

 

 

 

4.17 Subordinate Bus Number Register

The subordinate bus number register is programmed by the host system to indicate the highest numbered bus below the CardBus bus. The PCI7x21/PCI7x11 controller uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each CardBus controller function.

Bit

7

6

5

 

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

Subordinate bus number

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

RW

 

RW

RW

RW

RW

RW

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

 

0

0

0

0

0

 

Register:

Subordinate bus number

 

 

 

 

 

 

Offset:

1Ah

 

 

 

 

 

 

 

 

Type:

Read/Write

 

 

 

 

 

 

 

 

Default:

00h

 

 

 

 

 

 

 

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