Texas Instruments DM648 DSP User Manual
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TMS320DM647/DM648 DSP

DDR2 Memory Controller

User's Guide

Literature Number: SPRUEK5A

October 2007

2

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Contents

Preface ...............................................................................................................................

 

6

1

Introduction................................................................................................................

9

 

1.1

Purpose of the Peripheral .......................................................................................

9

 

1.2

Features ...........................................................................................................

9

 

1.3

Functional Block Diagram.......................................................................................

9

 

1.4

Industry Standard(s) Compliance Statement ...............................................................

10

2

Peripheral Architecture ..............................................................................................

11

 

2.1

Clock Control ....................................................................................................

11

 

2.2

Memory Map ....................................................................................................

11

 

2.3

Signal Descriptions .............................................................................................

11

 

2.4

Protocol Description(s).........................................................................................

13

 

2.5

Memory Width and Byte Alignment ..........................................................................

18

 

2.6

Address Mapping ...............................................................................................

19

 

2.7

DDR2 Memory Controller Interface ..........................................................................

22

 

2.8

Refresh Scheduling ............................................................................................

25

 

2.9

Self-Refresh Mode..............................................................................................

26

 

2.10

Reset Considerations ..........................................................................................

26

 

2.11

DDR2 SDRAM Memory Initialization.........................................................................

27

 

2.12

Interrupt Support................................................................................................

28

 

2.13

EDMA Event Support ..........................................................................................

28

 

2.14

Emulation Considerations .....................................................................................

28

3

Using the DDR2 Memory Controller .............................................................................

29

 

3.1

Connecting the DDR2 Memory Controller to DDR2 SDRAM .............................................

29

 

3.2

Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications .............

33

4

DDR2 Memory Controller Registers .............................................................................

36

 

4.1

Module ID and Revision Register (MIDR) ...................................................................

37

 

4.2

DDR2 Memory Controller Status Register (DMCSTAT)...................................................

37

 

4.3

SDRAM Configuration Register (SDCFG)...................................................................

38

 

4.4

SDRAM Refresh Control Register (SDRFC) ................................................................

40

 

4.5

SDRAM Timing 1 Register (SDTIM1)........................................................................

41

 

4.6

SDRAM Timing 2 Register (SDTIM2)........................................................................

43

 

4.7

Burst Priority Register (BPRIO)...............................................................................

44

 

4.8

DDR2 Memory Controller Control Register (DMCCTL) ...................................................

45

Appendix A

Revision History .............................................................................................

46

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Table of Contents

3

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List of Figures

 

1

DDR2 Memory Controller Block Diagram ...............................................................................

10

2

DDR2 Memory Controller Signals........................................................................................

12

3

DDR2 MRS and EMRS Command ......................................................................................

14

4

Refresh Command .........................................................................................................

15

5

ACTV Command ...........................................................................................................

15

6

DCAB Command ...........................................................................................................

16

7

DEAC Command ...........................................................................................................

16

8

DDR2 READ Command ...................................................................................................

17

9

DDR2 WRT Command ....................................................................................................

18

10

Byte Alignment..............................................................................................................

19

11

Logical Address-to-DDR2SDRAM Address Map for32-BitSDRAM...............................................

19

12

Logical Address-to-DDR2SDRAM Address Map for16-bitSDRAM................................................

20

13

Logical Address-to-DDR2 SDRAM Address Map ......................................................................

21

14

DDR2 SDRAM Column, Row, and Bank Access ......................................................................

22

15

DDR2 Memory Controller FIFO Block Diagram ........................................................................

23

16

DDR2 Memory Controller Reset Block Diagram .......................................................................

26

17

Connecting to Two 16-Bit DDR2 SDRAM Devices ....................................................................

30

18

Connecting to a Single 16-Bit DDR2 SDRAM Device .................................................................

31

19

Connecting to Two 8-Bit DDR2 SDRAM Devices......................................................................

32

20

Module ID and Revision Register (MIDR)...............................................................................

37

21

DDR2 Memory Controller Status Register (DMCSTAT) ..............................................................

37

22

SDRAM Configuration Register (SDCFG) ..............................................................................

38

23

SDRAM Refresh Control Register (SDRFC)............................................................................

40

24

SDRAM Timing 1 Register (SDTIM1) ...................................................................................

41

25

SDRAM Timing 2 Register (SDTIM2) ...................................................................................

43

26

Burst Priority Register (BPRIO) ..........................................................................................

44

27

DDR2 Memory Controller Control Register (DMCCTL) ...............................................................

45

4

List of Figures

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List of Tables

 

1

DDR2 Memory Controller Signal Descriptions .........................................................................

12

2

DDR2 SDRAM Commands ...............................................................................................

13

3

Truth Table for DDR2 SDRAM Commands ............................................................................

13

4

Addressable Memory Ranges ............................................................................................

18

5

Bank Configuration Register Fields for Address Mapping ............................................................

19

6

DDR2 Memory Controller FIFO Description ............................................................................

22

7

Refresh Urgency Levels ...................................................................................................

25

8

Reset Sources ..............................................................................................................

26

9

DDR2 SDRAM Mode Register Configuration...........................................................................

27

10

DDR2 SDRAM Extended Mode Register 1 Configuration ............................................................

27

11

SDCFG Configuration .....................................................................................................

33

12

DDR2 Memory Refresh Specification ...................................................................................

34

13

SDRFC Configuration......................................................................................................

34

14

SDTIM1 Configuration .....................................................................................................

34

15

SDTIM2 Configuration .....................................................................................................

35

16

DMCCTL Configuration....................................................................................................

35

17

DDR2 Memory Controller Registers .....................................................................................

36

18

Module ID and Revision Register (MIDR) Field Descriptions ........................................................

37

19

DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions ........................................

37

20

SDRAM Configuration Register (SDCFG) Field Descriptions ........................................................

38

21

SDRAM Refresh Control Register (SDRFC) Field Descriptions .....................................................

40

22

SDRAM Timing 1 Register (SDTIM1) Field Descriptions .............................................................

41

23

SDRAM Timing 2 Register (SDTIM2) Field Descriptions .............................................................

43

24

Burst Priority Register (BPRIO) Field Descriptions ....................................................................

44

25

DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions .........................................

45

A-1

Document Revision History ...............................................................................................

46

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List of Tables

5

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Preface

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About This Manual

This document describes the DDR2 memory controller in the TMS320DM647/DM648 Digital Signal Processor (DSP).

Notational Conventions

This document uses the following conventions.

Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

Registers in this document are shown in figures and described in tables.

Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

Reserved bits in a register figure designate a bit that is used for future device expansion.

Note: Acronyms 3PSW, CPSW, CPSW_3G, and 3pGSw are interchangeable and all refer to the 3 port gigabit switch.

Related Documentation From Texas Instruments

The following documents describe the TMS320DM647/DM648 Digital Signal Processor (DSP). Copies of these documents are available on the Internet at www.ti.com.Tip: Enter the literature number in the search box provided atwww.ti.com.

SPRS372 TMS320DM647/DM648 Digital Media Processor Data Manualdescribes the signals, specifications and electrical characteristics of the device.

SPRU732 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guidedescribes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.

SPRUEK5 TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guidedescribes the DDR2 memory controller in the TMS320DM647/DM648 Digital Signal Processor (DSP). The DDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices and standard Mobile DDR SDRAM devices.

SPRUEK6 TMS320DM647/DM648 DSP External Memory Interface (EMIF) User's Guidedescribes the operation of the asynchronous external memory interface (EMIF) in the TMS320DM647/DM648 Digital Signal Processor (DSP). The EMIF supports a glueless interface to a variety of external devices.

SPRUEK7 TMS320DM647/DM648 DSPGeneral-PurposeInput/Output (GPIO) User's Guidedescribes the general-purpose input/output (GPIO) peripheral in the TMS320DM647/DM648 Digital Signal Processor (DSP). The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input, you can detect the state of the input by reading the state of an internal register. When configured as an output, you can write to an internal register to control the state driven on the output pin.

6

Preface

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Related Documentation From Texas Instruments

SPRUEK8 TMS320DM647/DM648 DSPInter-IntegratedCircuit (I2C) Module User's Guidedescribes the inter-integrated circuit (I2C) peripheral in the TMS320DM647/DM648 Digital Signal Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices compliant with the I2C-bus specification and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to and from the DSP through the I2C peripheral. This document assumes the reader is familiar with the I2C-bus specification.

SPRUEL0 TMS320DM647/DM648 DSP64-BitTimer User's Guidedescribes the operation of the 64-bit timer in the TMS320DM647/DM648 Digital Signal Processor (DSP). The timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdog timer.

SPRUEL1 TMS320DM647/DM648 DSP Multichannel Audio Serial Port (McASP) User's Guidedescribes the multichannel audio serial port (McASP) in the TMS320DM647/DM648 Digital Signal Processor (DSP). The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).

SPRUEL2 TMS320DM647/DM648 DSP Enhanced DMA (EDMA) Controller User's Guidedescribes the operation of the enhanced direct memory access (EDMA3) controller in the TMS320DM647/DM648 Digital Signal Processor (DSP). The EDMA3 controller’s primary purpose is to service user-programmed data transfers between two memory-mapped slave endpoints on the DSP.

SPRUEL4 TMS320DM647/DM648 DSP Peripheral Component Interconnect (PCI) User's Guidedescribes the peripheral component interconnect (PCI) port in the TMS320DM647/DM648 Digital Signal Processor (DSP). The PCI port supports connection of the C642x DSP to a PCI host via the integrated PCI master/slave bus interface. The PCI port interfaces to the DSP via the enhanced DMA (EDMA) controller. This architecture allows for both PCI master and slave transactions, while keeping the EDMA channel resources available for other applications.

SPRUEL5 TMS320DM647/DM648 DSP Host Port Interface (UHPI) User's Guidedescribes the host port interface (HPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). The HPI is a parallel port through which a host processor can directly access the CPU memory space. The host device functions as a master to the interface, which increases ease of access. The host and CPU can exchange information via internal or external memory. The host also has direct access to memory-mapped peripherals. Connectivity to the CPU memory space is provided through the enhanced direct memory access (EDMA) controller.

SPRUEL8 TMS320DM647/DM648 DSP Universal Asynchronous Receiver/Transmitter (UART) User's Guidedescribes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM647/DM648 Digital Signal Processor (DSP). The UART peripheral performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data received from the CPU.

SPRUEL9 TMS320DM647/DM648 DSP VLYNQ Port User's Guidedescribes the VLYNQ port in the TMS320DM647/DM648 Digital Signal Processor (DSP). The VLYNQ port is a high-speed point-to-point serial interface for connecting to host processors and other VLYNQ compatible devices. It is a full-duplex serial bus where transmit and receive operations occur separately and simultaneously without interference.

SPRUEM1 TMS320DM647/DM648 DSP Video Port/VCXO Interpolated Control (VIC) Port User's Guidediscusses the video port and VCXO interpolated control (VIC) port in the TMS320DM647/DM648 Digital Signal Processor (DSP). The video port can operate as a video capture port, video display port, or transport channel interface (TCI) capture port. The VIC port provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. When the video port is used in TCI mode, the VIC port is used to control the system clock, VCXO, for MPEG transport channel.

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Related Documentation From Texas Instruments

SPRUEM2 TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guidediscusses the Serial Port Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). This reference guide provides the specifications for a 16-bit configurable, synchronous serial peripheral interface. The SPI is a programmable-length shift register, used for high speed communication between external peripherals or other DSPs.

SPRUEU6 — TMS320DM647/DM648 DSP Subsystem User'sGuidedescribes the subsystem in the TMS320DM647/DM648 Digital Signal Processor (DSP). The subsystem is responsible for performing digital signal processing for digital media applications. The subsystem acts as the overall system controller, responsible for handling many system functions such as system-level initialization, configuration, user interface, user command execution, connectivity functions, and overall system control.

SPRUF57 — TMS320DM647/DM648 DSP 3 Port Switch (3PSW) Ethernet Subsystem User'sGuidedescribes the operation of the 3 port switch (3PSW) ethernet subsystem in the TMS320DM647/DM648 Digital Signal Processor (DSP). The 3 port switch gigabit ethernet subsystem provides ethernet packet communication and can be configured as an ethernet switch (DM648 only). It provides the serial gigabit media independent interface (SGMII), the management data input output (MDIO) for physical layer device (PHY) management.

Trademarks

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