Texas Instruments Digital Signal Processor TMS320C6201 User Manual

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TMS320C6201

Digital Signal Processor

Silicon Errata

SPRZ153

November 2000

Copyright 2000, Texas Instruments Incorporated

TMS320C6201 Silicon Errata

SPRZ153

 

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Quality and Reliability Conditions . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

TMX Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

TMP Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

TMS Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Advisory 3.1.1 Issues When Pausing at a Block Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Advisory 3.1.2 DMA: Transfer Incomplete When Pausing a Synchronized Transfer in Mid-frame . . . . . . . . . . . . . .8 Advisory 3.1.3 DMA MultiframeSplit-modeTransfers Source Address Indexing Not Functional . . . . . . . . . . . . . . . 9 Advisory 3.1.4 DMA: Stopped Transfer Reprogrammed Does Not Wait for Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Advisory 3.1.5 DMA Freezes if Postincrement/Decrement Across Port Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Advisory 3.1.6 DMA Paused During Emulation Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Advisory 3.1.7 DMA: RSYNC = 10000b (DSPINT) Does Not Wait for Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Advisory 3.1.8 EMIF: Invalid SDRAM Access to Last 1K Byte of CE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Advisory 3.1.9 Cache During Emulation With Extremely Slow External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Advisory 3.0.8 EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Advisory 3.0.9 CPU: L2-unitLong Instructions Corrupted During Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Silicon Revision 2.1 Known Design Exceptions to Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Advisory 2.1.1 EMIF: CE Space Crossing on Continuous Request Not Allowed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Advisory 2.1.2 EMIF: SDRAM Invalid Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Advisory 2.1.4 DMA: RSYNC Cleared Late for Frame-synchronizedTransfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Advisory 2.1.5 McBSP: DXR to XSR Copy Not Generated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Advisory 2.1.6 DMASplit-modeEnd-of-frameIndexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Advisory 2.1.7 DMA Channel 0 MultiframeSplit-ModeIncompletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Advisory 2.1.8 Timer Clock Output Not Driven for External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Advisory 2.1.9Power-DownPin PD Not Set High forPower-Down2 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Advisory 2.1.10 EMIF: RBTR8 Bit Not Functional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Advisory 2.1.11 McBSP: Incorrect mLaw Companding Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Advisory 2.1.12 False Cache Hit – Extremely Rare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Advisory 2.1.13 EMIF: HOLD Feature Improvement on Revision 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Advisory 2.1.14 EMIF: HOLD Request Causes Problems With SDRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Advisory 2.1.15 DMA Priority Ignored by PBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Advisory 2.1.16 DMASplit-modeReceive Transfer Incomplete After Pause . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Advisory 2.1.17 DMA Multiframe Transfer Data Lost During Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Advisory 2.1.18 Bootload: HPI Feature Improvement on Revision 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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TMS320C6201 Silicon Errata

SPRZ153

Advisory 2.1.19 PMEMC: Branch from External to Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Advisory 2.1.21 DMA: DMA Data Block Corrupted After Start Zero Transfer Count . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

 

Advisory 2.0.1

Program Fetch: Cache Modes Not Functional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24

 

Advisory 2.0.2

Bootload: Boot from 16-Bitand32-BitAsynchronous ROMs Not Functional . . . . . . . . . . . . . . . . . .

24

 

Advisory 2.0.3

DMA Channel 0 Split Mode Combined With autoinitialization Performs Improper

 

 

 

Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24

 

Advisory 2.0.4

DMA/Program Fetch: Cannot DMA into Program Memory From External . . . . . . . . . . . . . . . . . . . .

24

 

Advisory 2.0.5

Data Access: Parallel Accesses to EMIF or Internal Peripheral Bus Location

 

 

 

Sequenced Wrong . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25

 

Advisory 2.0.7

EMIF: Reserved Fields Have Incorrect Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25

 

Advisory 2.0.8

EMIF: SDRAM Refresh/DCAB Not Performed Prior to HOLD Request Being Granted . . . . . . . . .

25

 

Advisory 2.0.9

McBSP New Block Interrupt Does Not Occur for Start of Block 0 . . . . . . . . . . . . . . . . . . . . . . . . . . .

26

 

Advisory 2.0.11

DMA/Internal Data Memory: First Load Data Corrupted When DMA in High Priority . . . . . . . . . . .

26

 

Advisory 2.0.12

McBSP: FRST Improved in 2.1 over 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26

 

Advisory 2.0.13 McBSP: XEMPTY Stays Low When DXR Written Late . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27

 

Advisory 2.0.14

EMIF: Multiple SDRAM CE Spaces: Invalid Access After Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . .

27

 

Advisory 2.0.18

DMA/Internal Data Memory: Conflict Data Corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27

 

Advisory 2.0.19

EMIF: Data Setup Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28

 

Advisory 2.0.24

EMIF Extremely Rare Cases Cause an Improper Refresh Cycle to Occur . . . . . . . . . . . . . . . . . . . .

28

7

Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28

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TMS320C6201 Silicon Errata

SPRZ153

1 Introduction

This document describes the silicon updates to the functional specifications for the TMS320C6201 silicon releases 3.1, 3.0, 2.1, and 2.0.

1.1Quality and Reliability Conditions

TMX Definition

Texas Instruments (TI) does not warranty either (1) electrical performance to specification, or (2) product reliability for products classified as “TMX.” By definition, the product has not completed data sheet verification or reliability performance qualification according to TI Quality Systems Specifications.

The mere fact that a “TMX” device was tested over a particular temperature and voltage ranges should not, in any way, be construed as a warranty of performance.

TMP Definition

TI does not warranty product reliability for products classified as “TMP.” By definition, the product has not completed reliability performance qualification according to TI Quality Systems Specifications; however, products are tested to a published electrical and mechanical specification.

TMS Definition

Fully-qualifiedproduction device.

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TMS320C6201 Silicon Errata

SPRZ153

1.2Revision Identification

The device revision can be determined by the lot trace code marked on the top of the package. The location for the lot trace codes for the GJL package is shown in Figure 1 and the revision numbers are listed in Table 1.

Figure 1. Example, Lot Trace Code for TMS320C6201

DSP

DSP

TMS320C6201GJL

TMS320C6201GJL

Cxx–YMLLLLS

C31–YMLLLLS

Lot trace code

Lot trace code with revision 3.1

NOTE: Qualified devices are marked with the letters “TMS” at the beginning of the device name, while nonqualified devices are marked with the letters “TMX” at the beginning of the device name.

Table 1. Lot Trace Number Names

Lot Trace Code

Silicon Revision

Comments

 

 

 

20

2.0

 

 

 

 

21

2.1

 

 

 

 

30

3.0

 

 

 

 

31

3.1

 

 

 

 

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TMS320C6201 Silicon Errata

SPRZ153

2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051)

Table 2. Timing Requirements for Interrupt Response Cycles

NO.

 

 

C6201B

UNIT

 

 

 

 

 

 

MIN

MAX

 

 

 

 

 

 

 

 

 

 

4

td(CKO2L-IACKV)

Delay time, CLKOUT2 low to IACK valid

–4

6

ns

5

td(CKO2L-INUMV)

Delay time, CLKOUT2 low to INUMx valid

 

6

ns

6

td(CKO2L-INUMIV)

Delay time, CLKOUT2 low to INUMx invalid

–4

 

ns

Table 3. JTAG Test-PortTiming

 

 

 

 

 

C6201,

 

NO.

 

 

 

 

C6201B

UNIT

 

 

 

 

 

 

 

 

 

 

 

MIN

MAX

 

 

 

 

 

 

 

 

 

1

Tc(TCK)

Cycle time, TCK

50

 

ns

4

Th(TCKH-TDIV)

 

 

 

 

 

 

Hold time, TDI/TMS/TRST

valid after TCK high

9

 

ns

Figure 2. SBSRAM Read Timing (1/2 Rate SSCLK) (See Note)

SSCLK

 

 

 

 

 

 

 

1

 

 

 

 

2

CE

 

 

 

 

 

 

BE_ [3:0]

3

 

 

 

4

 

BE1

BE2

BE3

BE4

 

 

 

 

 

 

5

 

 

 

6

 

EA [21:2]

A1

A2

A3

A4

 

 

 

 

 

7

8

 

 

 

 

 

 

 

 

ED [31:0]

 

 

Q1

Q2

Q3

Q4

 

 

 

 

9

 

 

 

10

 

SSADS

 

 

 

 

 

 

SSOE

11

 

 

 

 

12

 

 

 

 

 

 

SSWE

NOTE: The CEx output setup and hold times are specified to be accurate relative to the clock cycle to which they are referenced, since these timings are specified as minimums. However, the CE output setup and hold time may be greater than that shown

in the data sheet in multiples of P ns. In other words, for output setup time, the CEx transition from high to low may happen P, 2P,, or nP ns before the time specified by the data sheet. Similarly, for output hold time, the CExlow-to-hightransition may happen P, 2P,, or nP ns after the time specified by the data sheet. This is indicated by the period of uncertainty for specs 1 and 2 in Figure 2, and Figure 3.

6

TMS320C6201 Silicon Errata

 

 

 

SPRZ153

Figure 3. SBSRAM Write Timing (1/2 Rate SSCLK) (See Note)

SSCLK

 

 

 

 

 

1

 

 

2

CE

 

 

 

 

BE_ [3:0]

3

 

 

4

BE1

BE2

BE3

BE4

 

 

5

 

 

6

EA [21:2]

A1

A2

A3

A4

 

 

 

13

 

14

ED [31:0]

Q1

Q2

Q3

Q4

 

SSADS

 

9

 

10

 

 

 

 

SSOE

 

 

 

 

 

 

15

 

16

SSWE

 

 

 

 

NOTE: The CEx output setup and hold times are specified to be accurate relative to the clock cycle to which they are referenced, since these timings are specified as minimums. However, the CE output setup and hold time may be greater than that shown

in the data sheet in multiples of P ns. In other words, for output setup time, the CEx transition from high to low may happen P, 2P,, or nP ns before the time specified by the data sheet. Similarly, for output hold time, the CExlow-to-hightransition may happen P, 2P,, or nP ns after the time specified by the data sheet. This is indicated by the period of uncertainty for specs 1 and 2 in Figure 2, and Figure 3.

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TMS320C6201 Silicon Errata

SPRZ153

3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications

Advisory 3.1.1

Revision(s) Affected:

Details:

Workaround:

Advisory 3.1.2

Revision(s) Affected:

Details:

Workaround:

Issues When Pausing at a Block Boundary

3.1, 3.0, 2.1, and 2.0

The following problems exist when a DMA channel is paused at a block boundary:

DMA does not flush internal FIFO when a channel is paused across block boundary. As a result, data from old and new blocks of that channel are in FIFO simultaneously. This prevents other channels from using the FIFO for high performance until that channel is restarted. Data is not lost when that channel is started again. (Internal reference number C601299)

For DMA transfers with autoinitialization, if a channel is paused just as the last transfer in a block completes (just as the transfer counter reaches zero), none of the register reloads take place (count, source address, and destination address). When the same channel is restarted, the channel will not transfer anything due to the zero transfer count. This problem only occurs at block boundaries. (Internal reference number C601258)

Do not pause across block boundary if the internal FIFO is to be used by other channels for high performance. For DMA transfers with autoinitialization, if a channel is paused with a zero transfer count, manually reload all registers before restarting the channel.

DMA: Transfer Incomplete When Pausing a Synchronized Transfer in Mid-frame

3.1, 3.0, 2.1, and 2.0

If a frame-synchronizedtransfer is paused inmid-frameand then restarted again, a DMA channel does not continue the transfer. Instead, the channel waits for synchronization. If the channel is manually synchronized, it will properly complete the frame, but will immediately begin the transfer of the next frame. This behavior occurs for both a software pause (setting START = 10b) and for an emulation halt (with EMOD = 1). (Internal reference number C601257)

If pausing the DMA channel in software, do the following to restart:

1. Set the RSYNC bit in the Secondary Control Register.

2. Read the Transfer Count Register and then write back to Transfer Count Register. This enables the present frame to transfer but will wait for the next sync event to trigger the next frame transfer.

3. Set START to 01b or 11b.

If pausing the DMA channel with an emulation halt, do the following to restart:

1.Double-clickon the Transfer Count Register and hit enter (rewrite current transfer count).

2. Set the RSYNC STAT bit in the Secondary Control Register (change 0xXXXX4XXX to 0xXXXX1XXX).

3. Run.

NOTE: The sequence of 1 and 2 is critical for an emulator halt (EMOD = 1), but not for the software pause.

8

TMS320C6201 Silicon Errata

SPRZ153

Advisory 3.1.3

Revision(s) Affected:

Details:

Workaround:

Advisory 3.1.4

Revision(s) Affected:

Details:

Workaround:

Advisory 3.1.5

Revision(s) Affected:

Details:

Workaround:

DMA Multiframe Split-modeTransfers Source Address Indexing Not Functional

3.1, 3.0, 2.1, and 2.0

If a DMA channel is configured to do a multiframe split-modetransfer with SRC_DIR = Index (11b), the source address is always modified using the Element Index, even during the last element transfer of a frame. The transfer of the last element in a frame should index the source address using the Frame Index instead of the Element Index. DST_DIR = 11b functions properly. (Internal reference number C601256)

For multiframe transfers, use two DMA channels instead of using the split mode. Source Index works properly for non-split-modetransfers.

DMA: Stopped Transfer Reprogrammed Does Not Wait for Sync

3.1, 3.0, 2.1, and 2.0

If any non-synchronizedtransfer (e.g.,auto-inittransfer) is stopped, and then the same channel is programmed to do awrite-synchronizedtransfer (e.g.,split-modetransfer), the write transfer does not wait for the sync event. (Internal reference number C601261)

Perform a nonsynchronized dummy transfer of one element to/from the same location before starting the synchronized transfer.

DMA Freezes if Postincrement/Decrement Across Port Boundary

3.1, 3.0, 2.1, and 2.0

For any DMA transfers with source/destination address postincrement/decrement, if the last element to be transferred is aligned on a port boundary, then the DMA may freeze before transferring this element. A port boundary is the address boundary between external memory and program memory, between external memory and the peripheral address space, or between program memory and the peripheral address space.

The following conditions cause DMA to freeze:

For non-syncandframe-synctransfers: if a channel is paused after thesecond-to-lastelement is read, the DMA will freeze when the channel is then restarted with a request to the address at a port boundary.

For split-modetransfers orread/write-synctransfers: the DMA will freeze while transferring the element aligned on the port boundary. A continuous burst transfer withpost-increment/decrementsource/destination address does not exhibit this problem. (Internal reference number C601300)

Do not transfer to boundary addresses if the DMA source/destination address is post-incremented/

decremented.

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TMS320C6201 Silicon Errata

SPRZ153

Advisory 3.1.6

Revision(s) Affected:

Details:

Workaround:

Advisory 3.1.7

Revision(s) Affected:

Details:

Workaround:

Advisory 3.1.8

Revision(s) Affected:

Details:

Workaround:

DMA Paused During Emulation Halt

3.1, 3.0, 2.1, and 2.0

When running an autoinitialized transfer, the DMA write state machine is halted during an emulation halt regardless of the value of EMOD in the DMA Channel Primary Control Register. The read state machine functions properly in this case. The problem exists only at block boundaries. If EMOD = 1, this problem is irrelevant since the DMA channel is expected to pause during an emulation halt. (Internal reference number C601301)

There is no workaround for EMOD = 0. Expect DMA transfers to pause when the emulator stops the processor.

DMA: RSYNC = 10000b (DSPINT) Does Not Wait for Sync

3.1, 3.0, 2.1, and 2.0

If RSYNC in the DMA Channel Primary Control Register is set to host-porthost-to-DSPinterrupt (DSPINT – 10000b), the DMA channel would do the read transfer without waiting for the sync event. There is not a problem if WSYNC is set to DSPINT. (Internal reference number C601302)

Do not use synchronized DMA reads to DSPINT. If a DMA read is desired during a host-porthost-to-DSPinterrupt, set RSYNC in the Primary Control Register to one of the EXT_INT events instead (EXT_INT4 – EXT_INT7) and have the host trigger an interrupt on that pin rather than by writing to HPIC.

EMIF: Invalid SDRAM Access to Last 1K Byte of CE3

3.1, 3.0, 2.1, and 2.0

If 16M bytes of SDRAM (two 64M bits in a 1M X 16x4 organization) is used in CE3, you can have invalid accesses to the last 1K byte of CE3 (0x03FFFC00).

This occurs when the following is true:

After a DCAB (deactivate all pages) to all SDRAM CE spaces (forced by Refresh or MRS command)

The first access to CE3 is to the last page of CE3 (0x03FFFC00).

Then a page activate will not be issued to CE3. Since the SDRAM in CE3 is in a deactivated state at that point, invalid accesses will occur. (Internal reference number C630280)

Best Case: Avoid designing a board with a 64M-bit(1M X 16x4) SDRAM mapped into CE3.

10