Texas Instruments Digital Signal Processor SM320F2812-HT User Manual
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SM320F2812-HT

Digital Signal Processor

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SGUS062A

June 2009 –RevisedApril 2010

SM320F2812-HT

SGUS062A–JUNE2009–REVISEDAPRIL 2010www.ti.com

Contents

1

Features ...........................................................................................................................

 

11

 

1.1

SUPPORTS EXTREME TEMPERATURE APPLICATIONS .........................................................

12

2

Introduction ......................................................................................................................

 

13

 

2.1

Description .................................................................................................................

13

 

2.2

Device Summary ..........................................................................................................

14

 

2.3

Die Layout ..................................................................................................................

15

 

2.4

Pin Assignments ...........................................................................................................

16

 

2.5

Signal Descriptions ........................................................................................................

17

3

Functional Overview ..........................................................................................................

27

 

3.1

Memory Map ...............................................................................................................

28

 

3.2

Brief Descriptions ..........................................................................................................

31

 

 

3.2.1

C28x CPU .......................................................................................................

31

 

 

3.2.2

Memory Bus (Harvard Bus Architecture) ....................................................................

31

 

 

3.2.3

Peripheral Bus ..................................................................................................

31

 

 

3.2.4

Real-Time JTAG and Analysis ................................................................................

31

 

 

3.2.5

External Interface (XINTF) ....................................................................................

32

 

 

3.2.6

Flash .............................................................................................................

32

 

 

3.2.7

L0, L1, H0 SARAMs ............................................................................................

32

 

 

3.2.8

Boot ROM .......................................................................................................

32

 

 

3.2.9

Security ..........................................................................................................

33

 

 

3.2.10

Peripheral Interrupt Expansion (PIE) Block .................................................................

34

 

 

3.2.11

External Interrupts (XINT1, XINT2, XINT13, XNMI) ........................................................

34

 

 

3.2.12

Oscillator and PLL ..............................................................................................

34

 

 

3.2.13

Watchdog ........................................................................................................

34

 

 

3.2.14

Peripheral Clocking .............................................................................................

34

 

 

3.2.15

Low-Power Modes ..............................................................................................

34

 

 

3.2.16

Peripheral Frames 0, 1, 2 (PFn) ..............................................................................

35

 

 

3.2.17

General-Purpose Input/Output (GPIO) Multiplexer .........................................................

35

 

 

3.2.18

32-Bit CPU Timers (0, 1, 2) ...................................................................................

35

 

 

3.2.19

Control Peripherals .............................................................................................

35

 

 

3.2.20

Serial Port Peripherals .........................................................................................

36

 

3.3

Register Map ...............................................................................................................

36

 

3.4

Device Emulation Registers ..............................................................................................

39

 

3.5

External Interface, XINTF ................................................................................................

39

 

 

3.5.1

Timing Registers ................................................................................................

41

 

 

3.5.2

XREVISION Register ...........................................................................................

41

 

3.6

Interrupts ....................................................................................................................

42

 

 

3.6.1

External Interrupts ..............................................................................................

45

 

3.7

System Control ............................................................................................................

46

 

3.8

OSC and PLL Block .......................................................................................................

48

 

 

3.8.1

Loss of Input Clock .............................................................................................

49

 

3.9

PLL-Based Clock Module ................................................................................................

49

 

3.10 External Reference Oscillator Clock Option ...........................................................................

49

 

3.11

Watchdog Block ...........................................................................................................

50

 

3.12

Low-Power Modes Block .................................................................................................

51

 

 

 

 

2

Contents

 

Copyright © 2009–2010,Texas Instruments Incorporated

 

 

 

 

SM320F2812-HT

www.ti.com

 

 

SGUS062A –JUNE2009–REVISEDAPRIL 2010

4

Peripherals

.......................................................................................................................

52

 

4.1

32-Bit CPU-Timers 0/1/2 .................................................................................................

52

 

4.2

Event ...................................................................................Manager Modules (EVA, EVB)

55

 

 

4.2.1 ................................................................................

General - Purpose (GP) Timers

58

 

 

4.2.2 .............................................................................................

Full - Compare Units

58

 

 

4.2.3 ........................................................................

Programmable Deadband Generator

58

 

 

4.2.4 ..................................................................................

PWM Waveform Generation

58

 

 

4.2.5 ...................................................................................

Double Update PWM Mode

58

 

 

4.2.6 ...........................................................................................

PWM Characteristics

59

 

 

4.2.7 .....................................................................................................

Capture Unit

59

 

 

4.2.8 ...................................................................

Quadrature - Encoder Pulse (QEP) Circuit

59

 

 

4.2.9 ...........................................................................

External ADC Start - of - Conversion

59

 

4.3

Enhanced ...............................................................Analog-to-Digital Converter (ADC) Module

60

 

4.4

Enhanced ..................................................................Controller Area Network (eCAN) Module

65

 

4.5

Multichannel ..................................................................Buffered Serial Port (McBSP) Module

69

 

4.6

Serial .......................................................................Communications Interface (SCI) Module

73

 

4.7

Serial ...............................................................................Peripheral Interface (SPI) Module

76

 

4.8

GPIO .................................................................................................................MUX

79

5

Development ........................................................................................................Support

82

 

5.1

Device ...............................................................and Development Support Tool Nomenclature

82

 

5.2

Documentation ...................................................................................................Support

83

6

Electrical Specifications .....................................................................................................

85

 

6.1

Absolute ..............................................................................................Maximum Ratings

85

 

6.2

Recommended ..................................................................................Operating Conditions

86

 

6.3

Electrical .................................................................................................Characteristics

86

6.4Current Consumption by Power-SupplyPins Over Recommended Operating Conditions During

 

Low-Power Modes at 150-MHz SYSCLKOUT .........................................................................

 

88

6.5

Current Consumption Graphs ............................................................................................

 

89

6.6

Reducing Current Consumption .........................................................................................

 

90

6.7

Power Sequencing Requirements .......................................................................................

 

90

6.8

Signal Transition Levels ..................................................................................................

 

91

6.9

Timing Parameter Symbology ...........................................................................................

 

92

6.10

General Notes on Timing Parameters ..................................................................................

 

93

6.11

Test Load Circuit ..........................................................................................................

 

93

6.12

Device Clock Table ........................................................................................................

 

94

6.13

Clock Requirements and Characteristics ...............................................................................

 

94

 

6.13.1

Input Clock Requirements .....................................................................................

 

94

 

6.13.2

Output Clock Characteristics ..................................................................................

 

95

6.14

Reset Timing ...............................................................................................................

 

96

6.15

Low-Power Mode Wakeup Timing .....................................................................................

 

100

6.16

Event Manager Interface ................................................................................................

 

104

 

6.16.1

PWM Timing ...................................................................................................

 

104

 

6.16.2

Interrupt Timing ................................................................................................

 

106

6.17

General-Purpose Input/Output (GPIO) – Output Timing ............................................................

 

107

6.18

General-Purpose Input/Output (GPIO) – Input Timing ..............................................................

 

108

6.19

SPI Master Mode Timing ................................................................................................

 

109

 

 

 

Copyright © 2009–2010,Texas Instruments Incorporated

Contents

3

SM320F2812-HT

SGUS062A–JUNE2009–REVISEDAPRIL 2010

www.ti.com

 

6.20

SPI Slave Mode Timing .................................................................................................

113

 

6.21

External Interface (XINTF) Timing .....................................................................................

117

 

6.22

XINTF Signal Alignment to XCLKOUT ................................................................................

121

 

6.23

External Interface Read Timing ........................................................................................

122

 

6.24

External Interface Write Timing ........................................................................................

123

 

6.25

External Interface Ready-on-ReadTiming With One External Wait State.......................................

125

 

6.26

External Interface Ready-on-WriteTiming With One External Wait State........................................

128

 

6.27

 

and

 

 

131

 

XHOLD

XHOLDA

 

6.28

 

 

 

 

 

 

132

 

XHOLD/XHOLDA Timing ...............................................................................................

 

6.29

On-Chip Analog-to-Digital Converter ..................................................................................

134

 

 

6.29.1 ADC Absolute Maximum Ratings ...........................................................................

134

 

 

6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions ...........................

135

 

 

6.29.3 Current Consumption for Different ADC Configurations (at 25-MHzADCCLK)......................

136

 

 

6.29.4 ADC Power-Up Control Bit Timing ..........................................................................

137

 

 

6.29.5

 

Detailed Description ..........................................................................................

138

 

 

 

6.29.5.1

Reference Voltage ................................................................................

138

 

 

 

6.29.5.2

Analog Inputs .....................................................................................

138

 

 

 

6.29.5.3

Converter ..........................................................................................

138

 

 

 

6.29.5.4

Conversion Modes ...............................................................................

138

 

 

6.29.6 Sequential Sampling Mode (Single Channel) (SMODE = 0) ............................................

138

 

 

6.29.7 Simultaneous Sampling Mode (Dual-Channel)(SMODE = 1)..........................................

140

 

 

6.29.8 Definitions of Specifications and Terminology .............................................................

141

 

 

 

6.29.8.1

Integral Nonlinearity ..............................................................................

141

 

 

 

6.29.8.2

Differential Nonlinearity ..........................................................................

141

 

 

 

6.29.8.3

Zero Offset ........................................................................................

141

 

 

 

6.29.8.4

Gain Error .........................................................................................

141

 

 

 

 

6.29.8.5 Signal-to-NoiseRatio + Distortion (SINAD)...................................................

141

 

 

 

 

6.29.8.6 Effective Number of Bits (ENOB) ...............................................................

141

 

 

 

 

6.29.8.7 Total Harmonic Distortion (THD) ...............................................................

141

 

 

 

 

6.29.8.8 Spurious Free Dynamic Range (SFDR) .......................................................

141

 

6.30

Multichannel Buffered Serial Port (McBSP) Timing .................................................................

142

 

 

6.30.1 McBSP Transmit and Receive Timing ......................................................................

142

 

 

6.30.2 McBSP as SPI Master or Slave Timing ....................................................................

145

 

6.31

Flash Timing ..............................................................................................................

 

 

149

 

 

6.31.1

 

Recommended Operating Conditions ......................................................................

149

7

Mechanical Data ..............................................................................................................

 

 

151

4

Contents

Copyright © 2009–2010,Texas Instruments Incorporated

 

 

 

 

 

 

 

SM320F2812-HT

www.ti.com

SGUS062A – JUNE 2009 – REVISED APRIL 2010

 

 

List of Figures

 

 

2-1

SM320F2812 Die Layout ........................................................................................................

 

15

2-2

SM320F2812 172-Pin HFG CQFP (Top View)...............................................................................

 

16

3-1

Functional Block Diagram .......................................................................................................

 

28

3-2

F2812 Memory Map (See Notes A. Through G.) ............................................................................

 

28

3-3

External Interface Block Diagram ..............................................................................................

 

40

3-4

Interrupt Sources .................................................................................................................

 

42

3-5

Multiplexing of Interrupts Using the PIE Block ...............................................................................

 

43

3-6

Clock and Reset Domains ......................................................................................................

 

46

3-7

OSC and PLL Block..............................................................................................................

 

48

3-8

Recommended Crystal/Clock Connection ....................................................................................

 

49

3-9

Watchdog Module ................................................................................................................

 

50

4-1

CPU-Timers .......................................................................................................................

 

52

4-2

CPU-TimerInterrupts Signals and Output Signal (See Notes A. and B.)

.................................................

53

4-3

Event Manager A Functional Block Diagram (See Note A.) ................................................................

 

58

4-4

Block Diagram of the F2812 ADC Module ....................................................................................

 

61

4-5

ADC Pin Connections With Internal Reference (See Notes A and B).....................................................

 

62

4-6

ADC Pin Connections With External Reference .............................................................................

 

63

4-7

eCAN Block Diagram and Interface Circuit ...................................................................................

 

66

4-8

eCAN Memory Map ..............................................................................................................

 

67

4-9

McBSP Module With FIFO ......................................................................................................

 

70

4-10

Serial Communications Interface (SCI) Module Block Diagram............................................................

 

75

4-11

Serial Peripheral Interface Module Block Diagram (Slave Mode)..........................................................

 

78

4-12

GPIO/Peripheral Pin Multiplexing ..............................................................................................

 

81

5-1

28x Device Nomenclature.......................................................................................................

 

83

6-1

SM320F2812-HT Life Expectancy Curve .....................................................................................

 

87

6-2

Typical Current Consumption Over Frequency...............................................................................

 

89

6-3

Typical Power Consumption Over Frequency ................................................................................

 

90

6-4

F2812 Typical Power-UpandPower-DownSequence – Option 2........................................................

 

91

6-5

Output Levels .....................................................................................................................

 

92

6-6

Input Levels .......................................................................................................................

 

92

6-7

3.3-V Test Load Circuit ..........................................................................................................

 

93

6-8

Clock Timing ......................................................................................................................

 

96

6-9

 

 

= 0) (See Note A)

 

98

Power-onReset in Microcomputer Mode (XMP/MC

 

6-10

 

 

 

 

= 1)

 

99

Power-onReset in Microprocessor Mode (XMP/MC

 

6-11

Warm Reset in Microcomputer Mode..........................................................................................

 

99

6-12

Effect of Writing Into PLLCR Register .........................................................................................

 

99

6-13

IDLE Entry and Exit Timing....................................................................................................

 

100

6-14

STANDBY Entry and Exit Timing .............................................................................................

 

102

6-15

HALT Wakeup Using XNMI ...................................................................................................

 

104

6-16

PWM Output Timing ............................................................................................................

 

105

6-17

TDIRx Timing....................................................................................................................

 

106

6-18

 

Timing

 

106

EVASOC

 

6-19

 

Timing

 

106

EVBSOC

 

6-20

External Interrupt Timing.......................................................................................................

 

107

6-21

General-Purpose Output Timing ..............................................................................................

 

108

6-22

GPIO Input Qualifier – Example Diagram for QUALPRD = 1.............................................................

 

108

 

 

 

 

 

 

 

 

Copyright © 2009–2010,Texas Instruments Incorporated

List of Figures

5

SM320F2812-HT

SGUS062A–JUNE2009–REVISEDAPRIL 2010

www.ti.com

6-23

General-Purpose Input Timing ................................................................................................

109

6-24

SPI Master Mode External Timing (Clock Phase = 0) .....................................................................

110

6-25

SPI Master External Timing (Clock Phase = 1).............................................................................

112

6-26

SPI Slave Mode External Timing (Clock Phase = 0).......................................................................

114

6-27

SPI Slave Mode External Timing (Clock Phase = 1).......................................................................

116

6-28

Relationship Between XTIMCLK and SYSCLKOUT .......................................................................

120

6-29

Example Read Access .........................................................................................................

122

6-30

Example Write Access .........................................................................................................

124

6-31

Example Read With Synchronous XREADY Access ......................................................................

126

6-32

Example Read With Asynchronous XREADY Access .....................................................................

127

6-33

Write With Synchronous XREADY Access ..................................................................................

129

6-34

Write With Asynchronous XREADY Access ................................................................................

130

6-35

External Interface Hold Waveform............................................................................................

132

6-36

 

 

 

 

133

XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ..................................................

6-37

ADC Analog Input Impedance Model ........................................................................................

137

6-38

ADC Power-Up Control Bit Timing ...........................................................................................

137

6-39

Sequential Sampling Mode (Single-Channel) Timing ......................................................................

139

6-40

Simultaneous Sampling Mode Timing .......................................................................................

140

6-41

McBSP Receive Timing ........................................................................................................

144

6-42

McBSP Transmit Timing .......................................................................................................

144

6-43

McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ...................................................

145

6-44

McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ...................................................

146

6-45

McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ...................................................

147

6-46

McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ...................................................

148

6

List of Figures

Copyright © 2009–2010,Texas Instruments Incorporated

 

 

 

 

SM320F2812-HT

www.ti.com

SGUS062A –JUNE2009–REVISEDAPRIL 2010

 

 

 

List of Tables

 

 

2-1

Hardware Features...............................................................................................................

 

14

2-2

Bare Die Information .............................................................................................................

 

15

2-3

Signal Descriptions ..............................................................................................................

 

17

3-1

Addresses of Flash Sectors in F2812 .........................................................................................

 

29

3-2

Wait States ........................................................................................................................

 

30

3-3

Boot Mode Selection.............................................................................................................

 

33

3-4

Peripheral Frame 0 Registers ..................................................................................................

 

37

3-5

Peripheral Frame 1 Registers ..................................................................................................

 

37

3-6

Peripheral Frame 2 Registers ..................................................................................................

 

38

3-7

Device Emulation Registers.....................................................................................................

 

39

3-8

XINTF Configuration and Control Register Mappings .......................................................................

 

41

3-9

XREVISION Register Bit Definitions ...........................................................................................

 

41

3-10

PIE Peripheral Interrupts .......................................................................................................

 

43

3-11

PIE Configuration and Control Registers .....................................................................................

 

44

3-12

External Interrupts Registers ...................................................................................................

 

45

3-13

PLL, Clocking, Watchdog, and Low-Power Mode Registers ..............................................................

 

47

3-14

PLLCR Register Bit Definitions .................................................................................................

 

48

3-15

Possible PLL Configuration Modes ............................................................................................

 

49

3-16

F2812 Low-Power Modes .......................................................................................................

 

51

4-1

CPU-Timers 0, 1, 2 Configuration and Control Registers...................................................................

 

54

4-2

Module and Signal Names for EVA and EVB ................................................................................

 

55

4-3

EVA Registers ...................................................................................................................

 

56

4-4

ADC Registers ...................................................................................................................

 

64

4-5

3.3-V eCAN Transceivers for the SM320F2812 DSP .......................................................................

 

66

4-6

CAN Registers Map .............................................................................................................

 

68

4-7

McBSP Register Summary......................................................................................................

 

71

4-8

SCI-A Registers ..................................................................................................................

 

74

4-9

SCI-B Registers ..................................................................................................................

 

74

4-10

SPI Registers ....................................................................................................................

 

77

4-11

GPIO Mux Registers ............................................................................................................

 

79

4-12

GPIO Data Registers ............................................................................................................

 

80

6-1

Typical Current Consumption by Various Peripherals (at 150 MHz) .....................................................

 

90

6-2

Recommended Low-Dropout Regulators .....................................................................................

 

91

6-3

Clock Table and Nomenclature.................................................................................................

 

94

6-4

Input Clock Frequency ..........................................................................................................

 

94

6-5

XCLKIN Timing Requirements – PLL Bypassed or Enabled ..............................................................

 

95

6-6

XCLKIN Timing Requirements – PLL Disabled ..............................................................................

 

95

6-7

Possible PLL Configuration Modes ...........................................................................................

 

95

6-8

XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) .......................................................

 

95

6-9

Reset

 

Timing Requirements

 

96

(XRS)

 

6-10

IDLE Mode Switching Characteristics .......................................................................................

 

100

6-11

STANDBY Mode Switching Characteristics ................................................................................

 

101

6-12

HALT Mode Switching Characteristics ......................................................................................

 

103

6-13

PWM Switching Characteristics ..............................................................................................

 

105

6-14

Timer and Capture Unit Timing Requirements .............................................................................

 

105

6-15

External ADC Start-of-Conversion– EVA – Switching Characteristics.................................................

 

106

 

 

 

 

 

Copyright © 2009–2010,Texas Instruments Incorporated

List of Tables

7

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SGUS062A–JUNE2009–REVISEDAPRIL 2010

 

www.ti.com

6-16

 

External ADC Start-of-Conversion– EVB – Switching Characteristics

.................................................

106

6-17

 

Interrupt Switching Characteristics ...........................................................................................

 

106

6-18

 

Interrupt Timing Requirements................................................................................................

 

107

6-19

 

General-PurposeOutput Switching Characteristics ........................................................................

 

107

6-20

 

General-PurposeInput Timing Requirements ..............................................................................

 

108

6-21

 

SPI Master Mode External Timing (Clock Phase = 0) ....................................................................

 

109

6-22

 

SPI Master Mode External Timing (Clock Phase = 1) ....................................................................

 

111

6-23

 

SPI Slave Mode External Timing (Clock Phase = 0) ......................................................................

 

113

6-24

 

SPI Slave Mode External Timing (Clock Phase = 1) ......................................................................

 

115

6-25

 

Relationship Between Parameters Configured in XTIMING and Duration of Pulse ...................................

117

6-26

 

XTIMING Register Configuration Restrictions ..............................................................................

 

117

6-27

 

Valid and Invalid Timing .......................................................................................................

 

117

6-28

 

XTIMING Register Configuration Restrictions ..............................................................................

 

118

6-29

 

Valid and Invalid Timing when using Synchronous XREADY ............................................................

 

118

6-30

 

XTIMING Register Configuration Restrictions ..............................................................................

 

118

6-31

 

XTIMING Register Configuration Restrictions ..............................................................................

 

119

6-32

 

Asynchronous XREADY ......................................................................................................

 

119

6-33

 

XINTF Clock Configurations...................................................................................................

 

119

6-34

 

External Memory Interface Read Switching Characteristics .............................................................

 

122

6-35

 

External Memory Interface Read Timing Requirements ..................................................................

 

122

6-36

 

External Memory Interface Write Switching Characteristics ..............................................................

 

123

6-37

 

External Memory Interface Read Switching Characteristics (Ready-on-Read,1 Wait State) .......................

125

6-38

 

External Memory Interface Read Timing Requirements (Ready-on-Read,1 Wait State) ............................

125

6-39

 

Synchronous XREADY Timing Requirements (Ready-on-Read,1 Wait State) .......................................

125

6-40

 

Asynchronous XREADY Timing Requirements (Ready-on-Read,1 Wait State) ......................................

125

6-41

 

External Memory Interface Write Switching Characteristics (Ready-on-Write,1 Wait State) ........................

128

6-42

 

Synchronous XREADY Timing Requirements (Ready-on-Write,1 Wait State) .......................................

128

6-43

 

Asynchronous XREADY Timing Requirements (Ready-on-Write,1 Wait State) ......................................

128

6-44

 

 

 

 

 

 

132

 

XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ......................................................

 

6-45

 

 

 

 

 

 

133

 

XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) .................................................

 

6-46

 

DC Specifications ..............................................................................................................

 

135

6-47

 

AC Specifications ..............................................................................................................

 

136

6-48

 

Current Consumption ..........................................................................................................

 

136

6-49

 

ADC Power-UpDelays ........................................................................................................

 

137

6-50

 

Sequential Sampling Mode Timing ..........................................................................................

 

139

6-51

 

Simultaneous Sampling Mode Timing .......................................................................................

 

140

6-52

 

McBSP Timing Requirements ................................................................................................

 

142

6-53

 

McBSP Switching Characteristics ...........................................................................................

 

143

6-54

 

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ...............................

145

6-55

 

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ...........................

145

6-56

 

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ...............................

146

6-57

 

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ...........................

146

6-58

 

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ...............................

147

6-59

 

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ...........................

147

6-60

 

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ...............................

148

6-61

 

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ...........................

148

6-62

 

Flash Parameters at 150-MHzSYSCLKOUT ..............................................................................

 

149

6-63

 

Flash/OTP Access Timing ....................................................................................................

 

149

 

 

 

 

 

 

 

8

List of Tables

Copyright © 2009–2010,Texas Instruments Incorporated

 

 

SM320F2812-HT

www.ti.com

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6-64

Minimum Required Wait-Statesat Different Frequencies

................................................................ 149

Copyright © 2009–2010,Texas Instruments Incorporated

List of Tables

9

SM320F2812-HT

SGUS062A–JUNE2009–REVISEDAPRIL 2010

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10

List of Tables

Copyright © 2009–2010,Texas Instruments Incorporated

SM320F2812-HT

www.ti.com

SGUS062A –JUNE2009–REVISEDAPRIL 2010

Digital Signal Processor

Check for Samples: SM320F2812-HT

1 Features

High-PerformanceStatic CMOS Technology

150 MHz (6.67 ns Cycle Time)

Low Power (1.8 V Core at 135 MHz, 1.9 V, Core at 150 MHz, 3.3 V I/O) Design

3.3 V Flash Voltage

JTAG Boundary Scan Support(1)

High-Performance32 Bit CPU (TMS320C28x)

16 × 16 and 32 x 32 MAC Operations

16 × 16 Dual MAC

Harvard Bus Architecture

Atomic Operations

Fast Interrupt Response and Processing

Unified Memory Programming Model

4M Linear Program Address Reach

4M Linear Data Address Reach

Code-Efficient(in C/C++ and Assembly)

TMS320F24x/LF240x Processor Source Code Compatible

On-ChipMemory

Flash Devices: Up to 128K × 16 Flash (Four 8K × 16 and Six 16K × 16 Sectors)

ROM Devices: Up to 128K × 16 ROM

1K × 16 OTP ROM

L0 and L1: 2 Blocks of 4K × 16 Each Single-AccessRAM (SARAM)

H0: 1 Block of 8K × 16 SARAM

M0 and M1: 2 Blocks of 1K × 16 Each SARAM

Boot ROM (4K × 16)

With Software Boot Modes

Standard Math Tables

External Interface

Up to 1M Total Memory

Programmable Wait States

Programmable Read/Write Strobe Timing

Three Individual Chip Selects

Clock and System Control

Dynamic PLL Ratio Changes Supported

On-ChipOscillator

Watchdog Timer Module

Three External Interrupts

Peripheral Interrupt Expansion (PIE) Block That Supports 45 Peripheral Interrupts

128 Bit Security Key/Lock

Protects Flash/ROM/OTP and L0/L1 SARAM

Prevents Firmware Reverse Engineering

Three 32 Bit CPU Timers

Motor Control Peripherals

Two Event Managers (EVA, EVB)

Compatible to 240xA Devices

Serial Port Peripherals

Serial Peripheral Interface (SPI)

Two Serial Communications Interfaces (SCIs), Standard UART

Enhanced Controller Area Network (eCAN)

Multichannel Buffered Serial Port (McBSP) With SPI Mode

12 Bit ADC, 16 Channels

2 × 8 Channel Input Multiplexer

Two Sample-and-Hold

Single/Simultaneous Conversions

Fast Conversion Rate: 80 ns/12.5 MSPS

Up to 56 Individually Programmable, Multiplexed General-PurposeInput / Output (GPIO) Pins

Advanced Emulation Features

Analysis and Breakpoint Functions

Real-TimeDebug via Hardware

Development Tools Include

ANSI C/C++ Compiler/Assembler/Linker

Supports TMS320C24x™ /240x Instructions

Code Composer Studio™ IDE

DSP/BIOS™

JTAG Scan Controllers [Texas Instruments (TI) or Third-Party]

Evaluation Modules

Broad Third-PartyDigital Motor Control Support

Low-PowerModes and Power Savings

IDLE, STANDBY, HALT Modes Supported

Disable Individual Peripheral Clocks

(1)IEEE Standard 1149.1-1990,IEEE StandardTest-AccessPort

TMS320C24x, Code Composer Studio, DSP/BIOS, C28x, TMS320C2000, TMS320C54x, TMS320C55x, TMS320C28x are trademarks of Texas Instruments.

eZdsp is a trademark of Spectrum Digital Incorporated.

Copyright © 2009–2010,Texas Instruments Incorporated

Features

11

SM320F2812-HT

SGUS062A–JUNE2009–REVISEDAPRIL 2010

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1.1SUPPORTS EXTREME TEMPERATURE APPLICATIONS

Controlled Baseline

One Assembly/Test Site

One Fabrication Site

Available in Extreme (–55°C/220°C)Temperature Range(2)

Extended Product Life Cycle

Extended Product-ChangeNotification

Product Traceability

Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with design and process enhancements to maximize performance over extended temperatures.

(2)Custom temperature ranges available

12

Features

Copyright © 2009–2010,Texas Instruments Incorporated