Texas Instruments Digital Audio Processor with Codec TAS3002 User Manual

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TAS3002

Digital Audio Processor With Codec

Data

Manual

2001

Digital Audio: Digital Speakers

SLAS307B

IMPORTANT NOTICE

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TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, license, warranty or endorsement thereof.

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Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm

Mailing Address:

Texas Instruments

Post Office Box 655303

Dallas, Texas 75265

Copyright 2001, Texas Instruments Incorporated

1 Introduction

1.1 Description

The TAS3002 device is a system-on-a-chipthat replaces conventional analog equalization to perform digital parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provideshigh-quality,soft digital volume, bass, and treble control. All control parameters are uploaded from an outside MCU through the I2C slave port or from an external EEPROM through the I2C master port.

The TAS3002 device also has an integrated 24-bitstereo codec with twoI2C-selectable,single-endedinputs per channel.

The digital parametric equalization consists of seven cascaded, independent biquad filters per channel. Each biquad filter has five 24-bitcoefficients that can be configured into many different filter functions (such asband-pass,high-pass,andlow-pass).

The internal loudness contour algorithm can be controlled and programmed with an I2C command.

Dynamic range compression/expansion (DRCE) is programmable through the I2C port. The system designer can set the threshold, energy estimation time constant, compression ratio, and attack and decay time constants.

The TAS3002 device supports 13 serial interface formats (I2S, left justified, right justified) with data word lengths of 16, 18, 20, or 24 bits. The sampling frequency (fS) may be set to 32 kHz, 44.1 kHz, or 48 kHz. The 13 serial interface formats are listed and described in Section 2.1.

The TAS3002 device uses a system clock generated by the internal phase-lockedloop (PLL). The reference clock for the PLL is provided by an external master clock (MCLK) of 256fS or 512fS, or a 256fS crystal.

The TAS3002 device has six internally configurable general-purposeinput (GPI) terminals that control volume, bass, treble, and equalization. Each GPI terminal has a debounce algorithm that is programmed into the TAS3002 internal microcontroller.

1.2Features

Programmable seven-bandparametric equalization

Programmable digital volume control

Programmable digital bass and treble control

Programmable dynamic range compression/expansion (DRCE)

Programmable loudness contour/dynamic bass control

Configurable serial port for audio data

Two input data channels that can be mixed with digital data from the analog-to-digitalconverter (ADC) of the codec (analog input). These channels are controlled by I2C commands.

Three output data channels: Left and right data go through equalization; bass, treble, DRCE, and volume to SDOUT1; SDOUT2 mixes left and right data. SDOUT2 operates as a center channel or subwoofer channel. The output of the ADC is available for additional processing.

Capability to digitally mix left and right input channels for a monaural output to facilitate subwoofer operation

Serial I2C master/slave port that allows:

Downloading of control data to the device externally from the EEPROM or an I 2C master

Controlling other I 2C devices

1−1

Two I2C-selectable,single-endedanalog input stereo channels

Equalization bypass mode

Single 3.3-Vpower supply

Power down without reloading the coefficients

Sampling rates of 32 kHz, 44.1 kHz, or 48 kHz

Master clock frequency of 256fS or 512fS

Can have crystal input to replace MCLK. Crystal input frequency is 256fS.

Six GPI terminals for volume, bass, treble up/down control, mute, and selection of equalization filters

1.3Functional Block Diagram

Figure 1−1 is a block diagram showing the major functions of the TAS3002.

1−2

 

SS(REF)

REFM

REFP

RFILT

DD

SS

DD

SS

 

AV

V

V

V

AV

AV

DV

DV

AINRP

 

 

 

 

 

 

 

 

AINRM

 

 

 

 

 

 

 

 

RINA

 

Voltage

 

Analog

Digital

RINB

Reference

Supplies

Supplies

 

 

 

 

 

 

 

 

 

 

 

AINRP

 

 

 

 

 

 

AINRM

 

 

 

 

AINLP

 

 

24-Bit

 

 

 

SDOUT0

 

 

Stereo

 

 

 

 

AINLM

 

 

 

 

 

 

 

 

ADC

 

 

 

 

LINA

 

AINLP

 

 

 

 

LINB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AINLM

 

 

 

 

ALLPASS

 

 

 

 

 

 

 

VCOM

INPA

 

 

 

 

 

 

 

AOUTL

GPI5

 

 

 

 

 

 

 

Controller

 

 

 

 

 

 

 

GPI4

 

 

 

 

 

 

AOUTR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPI3

 

 

 

 

24-Bit

 

 

 

GPI2

 

 

 

 

 

 

 

 

 

 

 

Stereo DAC

 

 

 

GPI1

 

 

 

 

 

 

 

 

GPI0

 

 

 

 

 

 

 

 

 

L+R

 

 

 

 

 

 

L+R

 

 

 

 

 

 

 

SDOUT2

 

 

 

 

 

 

 

 

CS1

I Control

 

 

 

32-BitAudio Signal

 

 

C

 

 

 

 

SDA

 

 

 

 

Processor

 

2

 

 

 

 

 

SCL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDOUT1

PWR_DN

Control

L

R

 

32-BitAudio Signal

 

 

 

Processor

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST

 

 

SDATA

 

OSC/CLK

 

 

 

 

 

PLL

 

 

 

Control

 

Select

 

 

 

 

 

 

 

SDIN1 SDIN2

LRCLK/O SCLK/O

IFM/S

CLKSEL

XTALI/ MCLK XTALO MCLKO

CAP PLL

Figure 1−1. TAS3002 Block Diagram

1−3

1.4 Terminal Assignments

Figure 1−2 shows the terminal locations on the package outline, along with the signal name assigned to each terminal.

PACKAGE (TOP VIEW)

 

 

 

 

 

 

 

 

 

LINB

 

AINLP

 

AINLM

V

V

AINRM

AINRP

RINB RINA AOUTL VCOM

AOUTR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REFM

REFP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

48 47 46 45 44 43 42 41 40 39 38 37

 

 

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LINA

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

36

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AVDD

 

VRFILT

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

35

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AVSS(REF)

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

34

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPI5

 

AVSS

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

GPI4

 

 

INPA

 

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

GPI3

 

RESET

 

 

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPI2

 

 

CS1

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPI1

PWR_DN

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

29

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPI0

 

TEST

 

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALLPASS

CAP_PLL

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDOUT1

CLKSEL

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

 

MCLKO

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

 

SDOUT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

14 15 16 17 18 19

 

20 21 22 23 24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTALI/MCLK

 

XTALO

 

SCL

SDA

DV

DV

LRCLK/O

SCLK/O IFM/S SDIN1 SDIN2

SDOUT2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DD

SS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1−2. TAS3002 Terminal Assignments

1.5 Terminal Functions

Table 1−1 lists the terminals in alphanumeric order by signal name, along with the terminal number, terminal type, and a description of the terminal function.

 

 

 

Table 1−1. TAS3002 Terminal Functions

TERMINAL

 

I/O

DESCRIPTION

NAME

NO.

 

 

 

 

 

 

AINLM

46

I

ADC left channel analog input (antialias capacitor)

 

 

 

 

AINLP

47

I

ADC left channel analog input (antialias capacitor)

 

 

 

 

AINRM

43

I

ADC right channel analog input (antialias capacitor)

 

 

 

 

AINRP

42

I

ADC right channel analog input (antialias capacitor)

 

 

 

 

ALLPASS

27

I

Logic high bypasses equalization filters

 

 

 

 

AOUTL

39

O

Left channel analog output

 

 

 

 

AOUTR

37

O

Right channel analog output

 

 

 

 

AVDD

35

I

Analog power supply (3.3 V)

AVSS

4

I

Analog voltage ground

AVSS(REF)

3

I

Analog ground voltage reference

1−4

 

 

 

 

 

 

 

Table 1−1. TAS3002 Terminal Functions (Continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TERMINAL

 

I/O

 

 

 

DESCRIPTION

 

NAME

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CAP_PLL

10

I

Loop filter for internal phase-lockedloop (PLL)

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKSEL

11

I

Logic low selects 256 fS; logic high selects 512 fS MCLK

 

CS1

7

I

I2C address bit A0; low = 68h, high = 6Ah

 

DVDD

17

I

Digital power supply (3.3 V)

 

DVSS

18

I

Digital ground

 

GPI0

28

I

Switch input terminals

 

GPI1

29

 

 

 

 

 

 

 

GPI2

30

 

 

 

 

 

 

 

GPI3

31

 

 

 

 

 

 

 

GPI4

32

 

 

 

 

 

 

 

GPI5

33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

I

Digital audio I/O control (low = input; high = output)

 

IFM/S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

O

Low when analog input A is selected (will sink 4 mA)

 

INPA

 

 

 

 

 

 

 

 

 

 

 

 

 

LINA

1

I

Left channel analog input 1

 

 

 

 

 

 

 

 

 

 

 

LINB

48

I

Left channel analog input 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LRCLK/O

19

I/O

Left/right clock input/output (output when

IFM/S

is high)

 

MCLKO

12

O

MCLK output for slave devices

 

 

 

 

 

 

 

 

 

NC

34

 

No connection; Can be used as a printed circuit board routing channel

 

 

 

 

 

 

 

 

 

NC

36

 

No connection; Can be used as a printed circuit board routing channel

 

 

 

 

 

 

 

 

 

PWR_DN

8

I

Logic high places the TAS3002 device in power-downmode

 

 

 

 

 

 

 

 

 

 

 

 

6

I

Logic low resets the TAS3002 device to the initial state

 

RESET

 

 

 

 

 

 

 

 

 

RINA

40

I

Right channel analog input 1

 

 

 

 

 

 

 

 

RINB

41

I

Right channel analog input 2

 

 

 

 

 

 

 

 

SCL

15

I/O

I2C clock connection

 

 

 

 

 

 

SCLK/O

20

I/O

Shift (bit) clock input (output when

IFM/S

is high)

 

SDA

16

I/O

I2C data connection

 

SDIN1

22

I

Serial data input 1

 

 

 

 

 

 

SDIN2

23

I

Serial data input 2

 

 

 

 

 

 

SDOUT0

25

O

Serial data output from ADC

 

 

 

 

 

 

SDOUT1

26

O

Serial data output (from internal audio processing)

 

 

 

 

 

 

SDOUT2

24

O

Serial data output (a monaural mix of left and right, before processing)

 

 

 

 

 

 

TEST

9

I

Reserved manufacturing test terminal; connect to DVSS

 

VCOM

38

O

Digital-to-analogconvertermid-railsupply (decouple with parallel combination of 10- F and 0.1- F

 

 

 

 

 

 

 

capacitors)

 

 

 

 

 

 

VREFM

45

I

ADC minus voltage reference

 

VREFP

44

I

ADC plus voltage reference

 

VRFILT

2

O

Voltage reference low pass filter

 

XTALI/MCLK

13

I

Crystal or external MCLK input

 

 

 

 

 

 

XTALO

14

I

Crystal input (crystal is connected between terminals 13 and 14)

 

 

 

 

 

 

 

 

 

 

 

 

1−5

1−6

2 Audio Data Formats

2.1 Serial Interface Formats

The TAS3002 device works in master or slave mode.

In the master mode, terminal 21 (IFM/S) is tied high. This activates the master clock (MCLK) circuitry. A crystal can be connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external, TTL-compatibleMCLK can be connected to XTALI/MCLK. In that case, MCLK is outputs on terminal 12 (MCLKO), with terminals 19 (LRCLK/O) and 20 (SCLK/O) becoming outputs to drive slave devices.

In the slave mode, IFM/S is tied low. LRCLK/O and SCLK/O are inputs and the interface operates as a slave device requiring externally supplied MCLK, LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options for selecting the clock rates. If the 512fS MCLK rate is selected, terminal 11 (CLKSEL) is tied high and an MCLK rate of 512fS must be supplied. If the 256fS MCLK is selected, CLKSEL is tied low and an MCLK of 256fS must be supplied. In both cases, an LRCLK of 64SCLK must be supplied.

MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.

If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.

The TAS3002 device is compatible with 13 different serial interfaces. Available interface options are I2S, right justified, and left justified. Table 2−1 indicates how the 13 options are selected using the I2C bus and the main control register (MCR, I2C address 01h). All serial interface options at either 16, 18, 20, or 24 bits operate with SCLK at 64fS. Additionally, the16-bitmode operates at 32fS.

Table 2−1. Serial Interface Options

MODE

MCR BIT (6)

MCR BIT (5−4)

MCR BIT (1−0)

SERIAL INTERFACE

SDIN1, SDIN2, SDOUT1, SDOUT2, AND SDOUT0

 

 

 

 

 

 

 

 

 

0

0

00

00

16-bit,32 fS

1

1

00

00

16-bit,left justified, 64 fS

2

1

01

00

16-bit,right justified, 64 fS

3

1

10

00

16-bit,I2S, 64 f

 

 

 

 

S

4

1

00

01

18-bit,left justified, 64 fS

5

1

01

01

18-bit,right justified, 64 fS

6

1

10

01

18-bit,I2S, 64 fS

7

1

00

10

20-bit,left justified, 64 fS

8

1

01

10

20-bit,right justified, 64 fS

9

1

10

10

20-bit,I2S, 64 fS

10

1

00

11

24-bit,left justified, 64 fS

11

1

01

11

24-bit,right justified, 64 fS

12

1

10

11

24-bit,I2S, 64 fS

Figure 2−1 through Figure 2−3 illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the different interface protocols.

2−1

2.2 Digital Output Modes

The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3.

2.2.1MSB-First,Right-Justified,Serial-InterfaceFormat

The normal output mode for the MSB-first,right-justified,serial-interfaceformat is for 16, 18, 20, or 24 bits. Figure 2−1 shows the following characteristics of this protocol:

Left channel is transmitted when LRCLK is high.

The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK.

The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK.

If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.

SCLK

LRCLK = fS

SDIN

SDOUT

… …

MSB

… …

LSB

… …

MSB

… …

LSB

… …

MSB

… …

LSB

… …

MSB

… …

LSB

 

Left Channel

 

Right Channel

 

Figure 2−1. MSB-First,Right-Justified,Serial-InterfaceFormat

2−2