User's Guide
SLUU396A – January 2010 – Revised July 2010
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Contents |
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Introduction .................................................................................................................. |
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1.1 |
EVM Features ...................................................................................................... |
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1.2 |
General Description ................................................................................................ |
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1.3 |
I/O Description ...................................................................................................... |
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1.4 |
1.4 Controls and Key Parameters Setting ...................................................................... |
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1.5 |
Recommended Operating Conditions ........................................................................... |
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Test Summary ............................................................................................................... |
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2.1 |
Definitions ........................................................................................................... |
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2.2 |
Equipment ........................................................................................................... |
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2.3 |
Equipment Setup ................................................................................................... |
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2.4 |
Procedure ........................................................................................................... |
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PCB Layout Guideline ...................................................................................................... |
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Bill of Materials, Board Layout and Schematics ........................................................................ |
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4.1 |
Bill of Materials ..................................................................................................... |
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Board Layout ............................................................................................................... |
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Schematics ................................................................................................................. |
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List of Figures |
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Original Test Setup for HPA422 (bq2461x/bq2463x EVM)............................................................ |
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Top Layer................................................................................................................... |
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2nd Layer .................................................................................................................... |
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3rd Layer..................................................................................................................... |
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Bottom Layer ............................................................................................................... |
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Top Assembly .............................................................................................................. |
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Bottom Assembly .......................................................................................................... |
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Top Silkscreen ............................................................................................................. |
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Bottom Silkscreen ......................................................................................................... |
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bq2461x/bq2463x EVM Schematic ..................................................................................... |
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List of Tables |
1 |
I/O Description............................................................................................................... |
2 |
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Controls and Key Parameters Setting.................................................................................... |
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Recommended Operating Conditions .................................................................................... |
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4 |
Bill of Materials .............................................................................................................. |
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SLUU396A –January 2010 –Revised July 2010 |
bq2461x/bq2463x EVM (HPA422) Multi-Cell Synchronous Switch-Mode Charger |
1 |
Copyright © 2010, Texas Instruments Incorporated
Introduction |
www.ti.com |
•Evaluation Module For bq2461x/bq2463x
•High Efficiency Synchronous Buck Charger
•User-programmable up to 26V Battery Voltage
•AC Adapter Operating Range 5 V–28 V
•LED Indication for Control and Status Signals.
•Test Points for Key Signals Available for Testing Purpose. Easy Probe Hook-up.
•Jumpers Available. Easy to Change Connections.
The bq2461x is highly integrated Li-ion or Li-polymer switch-mode battery charge controllers. The bq2463x is highly integrated switch-mode battery charge controllers designed specifically to charge Lithium Phosphate battery chemistries.
They offer a constant-frequency synchronous PWM controller with high accuracy charge current and voltage regulation, adapter current regulation, termination, charge preconditioning, and charge status monitoring,
The bq2461x/bq2463x charges the battery in three phases: preconditioning, constant current, and constant voltage. Charge is terminated when the current reches a minimum user-selectable level. A programmable charge timer provides a safety backup for charge termination. The bq2461x/bq2463x automatically restarts the charge cycle if the battery voltage falls below an internal threshold, and enters a low-quiescent current sleep mode when the input voltage falls below the battery voltage.
The dynamic power management (DPM) function modifies the charge current depending on system load conditions, avoiding ac adapter overload.
High accuracy current sense amplifiers enable accurate measurement of the ac adapter current, allowing monitoring of overall system power.
For details, see bq24610 and bq24617 (SLUS892), bq24616 (SLUSA49) and bq2463x (SLUS894) data sheets.
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Table 1. I/O Description |
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Jack |
Description |
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J1–DCIN |
AC adapter, positive output |
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J1–GND |
AC adapter, negative output |
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J2–VEXT |
External power supply, positive output |
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J2–GND |
External power supply, negative output |
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J2–TTC |
Timer capacitor pin |
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J3–ACSET |
Input current program pin |
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J3–ISET1 |
Charge Current Program Pin |
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J3–ISET2 |
Pre-charge/Termination program pin |
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J3–GND |
Ground |
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Power Good (active low) |
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J–PG |
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J4–CHGEN |
Charge enable |
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J4–VREF |
IC reference voltage VREF |
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J4–TS |
Temperature Qualification Voltage Input |
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J5–VSYS |
Connected to system |
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J5–VBAT |
Connected to battery pack |
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2 |
bq2461x/bq2463x EVM (HPA422) Multi-Cell Synchronous Switch-Mode Charger |
SLUU396A –January 2010 –Revised July 2010 |
Copyright © 2010, Texas Instruments Incorporated
www.ti.com Introduction
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Table 1. I/O Description (continued) |
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Jack |
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Description |
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J5–GND |
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Ground |
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JP1–LOW |
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Ground |
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JP1–TTC |
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Timer capacitor pin |
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JP1–HI |
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Pull-up voltage source |
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JP2–HI |
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Pull-up voltage source |
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JP2–LEDPWR |
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LED Pull-up power line |
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JP3–VREF |
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IC reference voltage VREF |
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JP3–VPULLUP |
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Pull-up voltage source |
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JP3–EXT |
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External voltage supply from J2 |
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JP4–VCC |
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Pull-up voltage source of ACDRV and BATDRV LED logic circuit |
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JP4–VCOM |
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Q7 and Q11 common source |
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JP5–HI |
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Pull-up voltage source |
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JP5–CHGEN |
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Charge enable |
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Table 2. Controls and Key Parameters Setting
Jack |
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Description |
Factory Setting |
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TTC setting |
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JP1 |
1-2 |
: Connect TTC to GROUND (Disable termination and the safety timer) |
Jumper on 2-3 (TTC and VPULLUP) |
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2-3 |
: Connect TTC to VPULLUP (Allow termination, but disable the safety time) |
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2 floating: Allow termination, CTTC sets the safety timer |
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JP2 |
The pull-up power source supplies the LEDs when on. |
Jumper On |
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LED has no power source when off. |
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VPULLUP setting |
Jumper On 1-2 (VPULLUP and |
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JP3 |
1-2 |
: Connect VPULLUP to VREF |
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VREF) |
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2-3 |
: Connect VPULLUP to VEXT |
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JP4 |
The pull-up voltage source of ACDRV and BATDRV LED logic circuit. |
Jumper on |
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CHGEN setting |
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JP5 |
Jumper on: CHGEN to VPULLUP |
Jumper Off |
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Jumper off: CHGEN is set to low by pull down resistor. |
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Table 3. Recommended Operating Conditions
Symbol |
Description |
Min |
Typ |
Max |
Unit |
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24(617) |
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Supply voltage, VIN |
Input voltage from ac adapter input |
5 |
24 |
28 |
V |
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(610/616/63x) |
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Battery voltage, VBAT |
Voltage applied at VBAT terminal of J5 |
2.1 (61x) |
21 (61x) |
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V |
1.8 (63x) |
18 (63x) |
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Supply current, IAC |
Maximum input current from ac adapter |
0 |
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4.5 |
A |
input |
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Charge current, Ichrg |
Battery charge current |
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3 |
8 |
A |
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Operating junction |
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0 |
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125 |
°C |
temperature range, TJ |
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The bq2461x/bq2463x EVM board requires a regulated supply approximately 0.5 V minimum above the regulated voltage of the battery pack to a maximum input voltage of 28 VDC.
SLUU396A –January 2010 –Revised July 2010 |
bq2461x/bq2463x EVM (HPA422) Multi-Cell Synchronous Switch-Mode Charger |
3 |
Copyright © 2010, Texas Instruments Incorporated
Test Summary |
www.ti.com |
R25 and R28 can be changed to regulate output.
VBAT = 2.1V × [1+ R25/R28]; for bq2461x;
VBAT = 1.8V × [1+ R25/R28]; for bq2463x;
Adjust the input voltage as required. Output set to operate at 21V (bq2461x) or 18V (bq2463x) from the factory.
This procedure details how to configure the HPA422 evaluation board. On the test procedure the following naming conventions are followed. See the HPA422 schematic for details.
VXXX: |
External voltage supply name (VADP, VBT, VSBT) |
LOADW: |
External load name (LOADR, LOADI) |
V(TPyyy): |
Voltage at internal test point TPyyy. For example, V(TP12) means the voltage at TP12 |
V(Jxx): |
Voltage at jack terminal Jxx. |
V(TP(XXX)): |
Voltage at test point "XXX". For example, V(ACDET) means the voltage at the test |
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point which is marked as "ACDET". |
V(XXX, YYY): |
Voltage across point XXX and YYY. |
I(JXX(YYY)): |
Current going out from the YYY terminal of jack XX. |
Jxx(BBB): |
Terminal or pin BBB of jack xx |
Jxx ON: |
Internal jumper Jxx terminals are shorted |
Jxx OFF: |
Internal jumper Jxx terminals are open |
Jxx (-YY-) ON: |
Internal jumper Jxx adjacent terminals marked as "YY" are shorted |
Measure:→ A,B |
Check specified parameters A, B. If measured values are not within specified limits the |
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unit under test has failed. |
Observe → A,B |
Observe if A, B occur. If they do not occur, the unit under test has failed. |
Assembly drawings have location for jumpers, test points and individual components.
Power Supply #1 (PS#1): a power supply capable of supplying 30-V at 5-A is required.
Power Supply #2 (PS#2): a power supply capable of supplying 5-V at 1-A is required.
Power Supply #3 (PS#3): a power supply capable of supplying 5-V at 1-A is required.
A 30V (or above), 5A (or above) electronic load that can operate at constant current mode
A Kepco bipolar operational power supply/amplifier, 0 ±30V (or above), 0 ±6A (or above).
Tektronix TDS3054 scope or equivalent, 10X voltage probe.
4 |
bq2461x/bq2463x EVM (HPA422) Multi-Cell Synchronous Switch-Mode Charger |
SLUU396A –January 2010 –Revised July 2010 |
Copyright © 2010, Texas Instruments Incorporated
www.ti.com |
Test Summary |
Seven Fluke 75 multimeters, (equivalent or better)
Or: Four equivalent voltage meters and three equivalent current meters.
The current meters must be capable of measuring 5A+ current
1.Set the power supply #1 for 0V ± 100mVDC, 5.0 ± 0.1A current limit and then turn off supply.
2.Connect the output of power supply #1 in series with a current meter (multimeter) to J1 (VIN, GND).
3.Connect a voltage meter across J1 (VIN, GND).
4.Set the power supply #2 for 0V ± 100mVDC, 1.0 ± 0.1A current limit and then turn off supply.
5.Connect the output of the power supply #2 to J4 and J5 (TS, GND).
6.Connect Load #1 in series with a current meter to J5 (SYS, GND). Turn off Load #1
7.Connect Load #2 in series with a current meter to J5 (BAT, GND). Turn off Load #2.
8.Connect a voltage meter across J5 (BAT, GND).
9.Connect an oscilloscope's probe across J5 (BAT, GND)
10.Connect a voltage meter across J5 (SYS, GND).
11.JP1 (TTC and HI): ON, JP2: ON, JP3 (VPULLUP and VREF): ON, JP4: ON, JP5: OFF.
After the above steps, the test setup for HPA422 is shown in Figure 1.
Power supply #1
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bq24610/616/617/30 EVM |
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J1 |
HPA422 |
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PH |
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I |
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Isys |
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Iin |
ACPWR |
TP1 |
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TP12 |
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SYS |
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V |
ACPWR |
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I |
Load |
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PGND |
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J5 |
V |
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#1 |
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SYS |
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TP2 |
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BAT |
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I |
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U1 |
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Load |
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V |
Ibat |
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J3 |
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TP9 |
PGND |
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#2 |
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VCC |
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ACSET |
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ISET1 |
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JP4 |
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ISET2 |
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VBAT |
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Oscilloscope |
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GND |
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APPLICATION CIRCUIT |
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I |
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VREF |
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J2 |
JP3 |
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J4 |
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VEXT |
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VEXT |
HI |
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GND |
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PG |
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L |
JP1 |
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Power |
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TTC |
O |
JP2 |
JP5 |
STAT1 |
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VREF |
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sup ply #2 |
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TS |
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/ACDRV |
/BATDRV |
CE |
PG |
/STAT1 |
/STAT2 |
Figure 1. Original Test Setup for HPA422 (bq2461x/bq2463x EVM)
SLUU396A –January 2010 –Revised July 2010 |
bq2461x/bq2463x EVM (HPA422) Multi-Cell Synchronous Switch-Mode Charger |
5 |
Copyright © 2010, Texas Instruments Incorporated
Test Summary |
www.ti.com |
1.Make sure EQUIPMENT SETUP steps are followed. Turn on PS#2.
2.Turn on PS#1
Measure → V(J5(SYS)) = 0 ± 500mV Measure → V(TP(VREF)) = 0V ± 1000mV Measure → V(TP(REGN)) = 0V ± 500mV
3.Increase the output voltage on PS#1 until D5 (PG) on but do not exceed 5V. Set the power supply #2 to 1.8V ± 100mVDC
Measure → V(J1(VIN)) = 4.5V ± 0.5V Measure → V(J5(SYS)) = 4.5V ± 0.5V Measure → V(TP(VREF)) = 3.3V ± 200mV Measure → V(TP(REGN)) = 0V ± 500mV Measure → D4 (/ACDRV) on, D5 (PG) on
1.Increase the voltage of PS#1 until V(J1(VIN)) = 24V ± 0.1V. Measure → V(J5(BAT, GND)) = 0V ± 1V
2.Put JP5 on (Enable the charging). Observe → D3 (CE) on.
Measure → Peak V(J5(BAT)) = 21.0V ± 1V (bq2461x) Peak V(J5(BAT)) = 18.0V ± 1V (bq2463x)
Measure → V(TP(REGN)) = 6V ± 500mV
1.Take off JP5 (Disable the charging).
2.Connect the Load #2 in series with a current meter (multimeter) to J5 (BAT, GND). Make sure a voltage meter is connected across J5 (BAT, GND). Turn on the Load #2. Set the output voltage to 12V (bq2461x) or 2V (bq2463x).
3.Connect the output of the Load #1 in series with a current meter (multimeter) to J5 (SYS, GND). Make sure a voltage meter is connected across J5 (SYS, GND). Turn on the power of the Load #1. Set the load current to 3.0A ± 50mA but disable the load #1. The setup is now like Figure 1 for HPA422. Make sure Ibat = 0A ± 10mA and Isys = 0A ± 10mA.
4.Put JP5 on (Enable the charging). Observe → D3 (CE) on
Measure → Ibat = 300mA ± 200mA (bq2461x) Ibat = 125mA ± 60mA (bq2463x)
Observe → D7 (STAT1) on; D8 (STAT2) off.
5.Set the Load #2 output voltage to 16.5V. Measure → Ibat = 3000mA ± 300mA Observe → D7 (STAT1) on; D8 (STAT2) off.
6.Enable the output of the Load #1
Measure → Isys = 3000mA ± 200mA, Ibat = 1400mA ± 500mA, Iin = 4000mA ± 500mA
7.Turn off the Load #1.
Measure → Isys = 0 ± 100mA, Ibat = 3000mA ± 300mA.
8.Increase the Load #2 output voltage from 16.5V to 22V (61x) or 19V (63x). Measure → Isys = 0 ± 100mA, Ibat = 0mA ± 100mA.
Observe → D7 (STAT1) off; D8 (STAT2) on.
9.Decrease the Load #2 output voltage back to 16.5V. Observe → D7 (STAT1) on; D8 (STAT2) off.
6 |
bq2461x/bq2463x EVM (HPA422) Multi-Cell Synchronous Switch-Mode Charger |
SLUU396A –January 2010 –Revised July 2010 |
Copyright © 2010, Texas Instruments Incorporated
www.ti.com |
PCB Layout Guideline |
2.4.4Charger Cut-Off by Thermistor
1.Slowly increase the output voltage of PS2 until Ibat = 0 ± 10mA. Measure → V(J4(TS)) = 2.44V ± 200mV
Observe → D7 (STAT1) off; D8 (STAT2) off.
2.Slowly decrease the output voltage of PS2 to 1.4V ± 0.1V. Measure → V(J4(TS)) = 1.4V ± 100mV
Measure → Ibat = 3000mA ± 300mA (bq24610/617) Ibat = 0mA ± 100mA (bq24616)
Ibat = 375mA ± 150mA (bq2463x)
Observe → D7 (STAT1) on; D8 (STAT2) off (bq24610/617/630) Observe → D7 (STAT1) off; D8 (STAT2) off (bq24616)
3.Slowly decrease the output voltage of PS2.
Charge will resume. Continue to decrease the output voltage of PS2 slowly until Ibat = 0 ±10mA. Measure → V(J4(TS)) = 1.14V ± 200mV
Observe → D7 (STAT1) off; D8 (STAT2) off.
4.Slowly increase the output voltage of PS2 to 1.8V ± 100mV. Measure → Ibat = 3000mA ± 200mA
Observe → D7 (STAT1) on; D8 (STAT2) off.
1.Take off JP5 (Disable the charging) Observe → D3 (CE) off; D7 (STAT1) off.
2.Set JP3 Jumper On 2-3 (VPULLUP and VEXT). Connect the output of the power supply #3 to J2(VEXT, GND). Set the power supply #3 for 3.3V ± 200mVDC, 1.0 ± 0.1A current limit.
3.Set the Load #2 output voltage to 16.5V ± 500mV.
4.Measure → V(J5(SYS)) = 24V ± 1V (adapter connected to system)
Observe → D4 (ACDRV) on, D6 (BATDRV) off, D5 (PG) on, D7 (STAT1) off, D8 (STAT2) off.
5.Turn off PS#1.
6.Measure → V(J5(SYS)) = 16.5V ± 0.5V (battery connected to system)
7.Observe → D4 (ACDRV) off, D6 (BATDRV) on, D5 (PG) off, D7 (STAT1) off, D8 (STAT2) off.
8.Turn off power supply #2 and #3. Set JP3 on 1-2 (VPULLUP and VREF).
3PCB Layout Guideline
1.It is critical that the exposed power pad on the backside of the bq2461x/bq2463x package be soldered to the PCB ground. Make sure there are sufficient thermal vias right underneath the IC, connecting to the ground plane on the other layers.
2.The control stage and the power stage should be routed separately. At each layer, the signal ground and the power ground are connected only at the power pad.
3.AC current sense resistor must be connected to ACP and ACN with a Kelvin contact. The area of this loop must be minimized. The decoupling capacitors for these pins should be placed as close to the IC as possible.
4.Charge current sense resistor must be connected to SRP, SRN with a Kelvin contact. The area of this loop must be minimized. The decoupling capacitors for these pins should be placed as close to the IC as possible.
5.Decoupling capacitors for DCIN, VREF, VCC, REGN should make the interconnections to the IC as short as possible.
6.Decoupling capacitors for BAT must be placed close to the corresponding IC pins and make the interconnections to the IC as short as possible.
7.Decoupling capacitor(s) for the charger input must be placed close to top buck FET's drain and bottom buck FET’s source.
SLUU396A –January 2010 –Revised July 2010 |
bq2461x/bq2463x EVM (HPA422) Multi-Cell Synchronous Switch-Mode Charger |
7 |
Copyright © 2010, Texas Instruments Incorporated