Texas Instruments 45 User Manual

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ADS5525/27/45/46/47 EVM User

Guide

User's Guide

November 2006

SLWU028B

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Contents

1

Overview....................................................................................................................

5

 

1.1

EVM Basic Functions ............................................................................................

5

2

EVM Quick Start Guide ................................................................................................

6

 

2.1

EVM LVDS Output Mode Quick Start (Default) ..............................................................

6

 

2.2

EVM CMOS Output Mode Quick Start ........................................................................

6

3

Circuit Description ......................................................................................................

7

 

3.1

Schematic Diagram ..............................................................................................

7

 

3.2

Circuit Function...................................................................................................

7

4

Expansion Options ....................................................................................................

13

 

4.1

Custom FPGA Code ...........................................................................................

13

 

4.2

Expansion Slot ..................................................................................................

13

 

4.3

Optional USB SPI Interface ...................................................................................

13

5

Physical Description ..................................................................................................

14

 

5.1

PCB Layout......................................................................................................

14

 

5.2

Bill of Materials..................................................................................................

20

 

5.3

PCB Schematics................................................................................................

25

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Table of Contents

3

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List of Figures

 

1

ADS5547 SNR Performance vs Decoupling .............................................................................

8

2

THS4509 + ADS5545 EVM Performance ................................................................................

9

3

Eye Diagram of Data on Header J4......................................................................................

11

4

Top Layer....................................................................................................................

14

5

Layer 2, Ground Plane ....................................................................................................

15

6

Layer 3, Power Plane #1 ..................................................................................................

16

7

Layer 4, Power Plane #2 ..................................................................................................

17

8

Layer 5, Ground Plane ....................................................................................................

18

9

Layer 6, Bottom Layer .....................................................................................................

19

 

List of Tables

 

1

DIP Switch SW1 .............................................................................................................

7

2

EVM Power Options .........................................................................................................

8

3

Output Connector J4.......................................................................................................

10

4

Test Points ..................................................................................................................

12

5

Bill of Materials .............................................................................................................

21

4

List of Figures

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User's Guide

SLWU028B – January 2006 – Revised November 2006

1Overview

This manual assists users in using the ADS5525/27/45/46/47 evaluation module (EVM) for evaluating the performance of the ADS5525/27/45/46/47 (ADCs). The EVM provides a powerful and robust capability in evaluation of the many features of the ADCs and the performance of the device der many conditions.

1.1EVM Basic Functions

Analog input to the ADC is provided via external SMA connectors. The user supplies a single-endedinput, which is converted into a differential signal. One input path uses a differential amplifier, while the other input istransformer-coupled.

The EVM provides an external SMA connector for input of the ADC clock. The single-endedinput is converted into a differential signal at the input of the device.

Digital output from the EVM is via a 40-pinconnector.

Power connections to the EVM are via banana jack sockets. Separate sockets are provided for the ADC analog and digital supplies, the FPGA supply, and the differential amplifier supply.

CAUTION

Exceeding the maximum input voltages can damage EVM components. Undervoltage may cause improper operation of some or all of the EVM components.

Xilinx, Spartan, WebPACK are trademarks of Xilinx, Inc.

All other trademarks are the property of their respective owners.

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EVM Quick Start Guide

2EVM Quick Start Guide

The ADC has two basic modes of output operation, ensuring compatibility in a broad range of systems. Follow the steps below to get the EVM operating quickly with the ADC in either DDR LVDS output mode or CMOS output mode.

Note: Follow the steps in the listed order; not doing so could result in improper operation.

2.1EVM LVDS Output Mode Quick Start (Default)

1.Ensure a jumper is installed between pins 1 and 2 on JP2.

2.Ensure DIP switch SW1, switch 2 is set to LVDS.

3.Ensure DIP switch SW1, switch 8 is set to PARALLEL.

4.Use a regulated power supply to provide 3.3 VDC to the ADC at J11 and J15, with the corresponding returns connected to J9 and J16.

5.Use a regulated power supply to provide a 5-VDCinput to J14, while connecting the return to J17.

6.Provide a filtered, low-phase-noise,sinusoidal1.5-Vrms,170-MHzclock to J7.

7.Provide a filtered, sinusoidal analog input to J3.

8.Using a logic analyzer and Table 3 in this manual, monitor the ADC output on J4.

2.2EVM CMOS Output Mode Quick Start

1.Ensure a jumper is installed between pins 2 and 3 on JP2.

2.Ensure DIP switch SW1, switch 2 is set to CMOS.

3.Ensure DIP switch SW1, switch 8 is set to PARALLEL.

4.Use a regulated power supply to provide 3.3 VDC to the ADC at J11 and J15, with the corresponding returns connected to J9 and J16.

5.Use a regulated power supply to provide a 5-VDCinput to J14, while connecting the return to J17.

6.Provide a low-phase-noise,sinusoidal1.5-Vrms,170-MHzclock to J7.

7.Provide a filtered sinusoidal analog input to J3.

8.Briefly depress S1, which resets the EVM.

9.Using a logic analyzer and Table 3 in this manual, monitor the ADC output on J4.

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Circuit Description

3 Circuit Description

3.1Schematic Diagram

The schematic diagram for the EVM is in Section 5.3 of this document.

3.2Circuit Function

The following paragraphs describe the function of individual circuits. See the data sheet for complete device operating characteristics.

3.2.1Configuration Options

The EVM provides a DIP switch, SW1, to control many of the modes of operation when the EVM is configured for parallel-modeoperation.Table 1 describes the functionality of the DIP switches.

Note: When the device is configured forserial-modeoperation (SW1, switch 8), the DIP settings on SW1, switch 1 through SW1, switch 7 are ignored.

Table 1. DIP Switch SW1

SW1 SWITCH

OFF

ON

DESCRIPTION

NUMBER

 

 

 

1

2s complement

Offset binary

Determines device output format

2

LVDS

CMOS

Determines device output mode

3

Reserved

Reserved

Reserved

4

Internal reference

External reference

When set to External Reference, ADC uses common-mode

 

 

 

voltage on TP1.

5

Edge = 1

Edge = 2

Allows for output edge programmability

6

Edge = 3

Edge = 4

Allows for output edge programmability

7

Normal

Power down

Allows for power down

8

Serial

Parallel

Determines mode for register interface

By switching SW1, switch 8 to OFF, the ADC operates in serial mode, using its programmed register contents. A complete register map can be found in the device datasheet. Three pins on header J6 have been reserved for programming the device while it operates in serial mode. To program the device registers using header J6, place SCLK on pin 21, SDATA on pin 23, and SEN on pin 25. A pattern generator can be used to generate the patterns needed for programming. Alternatively, TI provides an optional USB daughtercard that plugs into the expansion slot of the EVM. The USB daughtercard allows ADC register control via a software package loaded onto the PC.

3.2.2Power

Power is supplied to the EVM via banana jack sockets. The EVM offers the capability to supply analog and digital 3.3 V independently to the ADC. Table 2 offers a snapshot of thepower-supplyoptions. All supply connections are required for default operation, except J12, J10, J13, and J20.

The EVM provides local decoupling for the ADC; however, the ADC features internal decoupling, and in many cases minimal external decoupling can be used without loss in performance. Users are encouraged to experiment to find the optimal amount of external decoupling required for their application. Figure 1 shows the ADS5547LVDS-modeperformance with all of the decoupling capacitors installed and the performance with C4, C5, C6, C7, C8, C9, and C10 removed. By default, the EVM comes with all of the decoupling capacitors installed.

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Circuit Description

Table 2. EVM Power Options

BANANA JACK

NAME

VOLTAGE

DESCRIPTION

J9

Device AGND

GND

 

J10

AGND

GND

 

J11

Device AVDD

3.3

Device analog supply

J12

Amplifier negative

–5

THS4509 Vs– supply

 

rail

 

 

J13

Amplifier positive rail

5

THS4509 Vs+ supply

J14

Auxiliary power

5

Supplies power to all peripheral circuitry including the FPGA

 

 

 

and PROM. Voltages rails are created by using TI'sTPS75003

 

 

 

voltage regulator.

J15

Device DVDD

3.3

Device internal digital output supply

J16

DGND

GND

 

J17

DGND

GND

 

J20

 

 

If TP11, TP12, and TP13 are tied low, the TPS75003 is

 

 

 

disabled. In this case, one can supply 3.3 V to pin 1, 1.2 V to

pin 2, and 2.2 V to pin 3 of J20 while connecting the ground to J17.

 

74

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 Decoupling Cap

 

 

− dBFS

73

 

 

 

 

 

 

 

 

 

 

 

72

 

 

 

 

 

 

 

 

 

 

 

Ratio

 

 

 

 

 

Baseline-AllDecoupling Caps

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal-to-Noise

71

 

 

 

 

 

 

 

 

 

 

 

70

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SNR −

69

 

 

 

 

 

 

 

 

 

 

 

 

68

 

 

 

 

 

 

 

 

 

 

 

 

9.97

19.94

30.13

40.33

50.13

60.13

69.59

79.87

89.75

100.33

130.13

170.13

 

 

 

 

 

fIN − Input Frequency − MHz

 

 

 

G001

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1. ADS5547 SNR Performance vs Decoupling

3.2.3Analog Inputs

The EVM can be configured to provide the ADC with either transformer-coupledor differential amplifier inputs from asingle-endedsource. The inputs are provided via SMA connector J3 fortransformer-coupledinput or SMA connector J1 for differential amplifier input. To set up for one of these options, the EVM must be configured as follows:

1.For a 1:1 transformer-coupledinput to the ADC, asingle-endedsource is connected to J3. Confirm that SJP4 has pins 2 and 3 shorted, and that SJP5 has pins 2 and 3 shorted. The transformer used, theMini-CircuitsTC4-1W,forms an inherentband-passfilter with a pass band from 3 MHz to 800 MHz. This is the default configuration for the EVM.

2.One can use a TI THS4509 amplifier to drive the ADC by applying an input to J1. Reconfigure SJP4 and SJP5 such that both have pins 1 and 2 shorted. A 5-VDCsupply must be connected to the board to provide power to U3 for this configuration.

The THS4509 amplifier path converts a single-endedsignal presented on J1 into a differential signal.

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Circuit Description

The schematics present various interface options between the amplifier and the ADC. Depending on the input frequencies of interest, further performance optimization can be had by designing a corresponding filter. In its default configuration, R43, R44, and C119 form a first-order,low-passfilter with a cutoff frequency of 70 MHz.Figure 2 shows the performance of the ADS5545 using the THS4509 path.

Amplitude − dBFS

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−60

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−70

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−80

 

 

 

 

 

 

3

 

 

 

5

 

 

 

x

 

 

 

 

−90

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−110

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−120

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−130

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−135

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

f − Frequency − MHz

G002

Figure 2. THS4509 + ADS5545 EVM Performance

3.2.4Clock Input

A single-ended,harmonically filtered,low-phase-noise,1.5-Vrmssinusoidal input should be applied to J7. The frequency must not exceed the device specification. In the EVM default configuration, both SPJ1 and SJP2 must have pins 1 and 2 shorted.

In the board default configuration, the transformer provides single-endedto differential conversion. The transformer has an impedance ratio of 4.

3.2.5Digital Outputs

For compatibility with a broad range of logic analyzers, the EVM outputs 3.3-Vparallel CMOS data on header J4, independent of the ADC operational mode. TheXilinx™Spartan™-3EFPGA provides the necessary translation, and it configures itself using one of two different logic files stored in the PROM, based on the EVM configuration. The CMOS data output of the FPGA is contained in data header J4 and is a standard40-pinheader on a100-milgrid, which allows easy connection to a logic analyzer. The connector pinout is listed inTable 3. For quick setup, the eye diagram is shown inFigure 3. No setup orhold-timeadjustments must be made to the logic analyzer if using the rising edge of the output clock to latch in the data.

Note: The eye diagram shown is the output of the FPGA at 210 MSPS, not that of the ADC. For the ADC output timing, see the respective device data sheet.

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Circuit Description

Table 3. Output Connector J4

J4 PIN

ADS5525/27 DESCRIPTION

ADS5545/46/47 DESCRIPTION

1

CLK

CLK

2

GND

GND

3

NC

NC

4

GND

GND

5

Reserved

Reserved

6

GND

GND

7

Reserved

Reserved

8

GND

GND

9

NC

Data bit 0 (LSB)

10

GND

GND

11

NC

Data bit 1

12

GND

GND

13

Data bit 0 (LSB)

Data bit 2

14

GND

GND

15

Data bit 1

Data bit 3

16

GND

GND

17

Data bit 2

Data bit 4

18

GND

GND

19

Data bit 3

Data bit 5

20

GND

GND

21

Data bit 4

Data bit 6

22

GND

GND

23

Data bit 5

Data bit 7

24

GND

GND

25

Data bit 6

Data bit 8

26

GND

GND

27

Data bit 7

Data bit 9

28

GND

GND

29

Data bit 8

Data bit 10

30

GND

GND

31

Data bit 9

Data bit 11

32

GND

GND

33

Data bit 10

Data bit 12

34

GND

GND

35

Data bit 11 (MSB)

Data bit 13 (MSB)

36

GND

GND

37

NC

NC

38

GND

GND

39

NC

NC

40

GND

GND

10

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