LG 55LA620S, 55LA620V, 55LA6208 Service manual

5 (2)

Printed in KoreaP/NO : MFL67727116 (1302-REV00)

CHASSIS : LD33B

MODEL : 55LA62** 55LA62**-Z*

CAUTION

BEFORE SERVICING THE CHASSIS,

READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

LED TV

SERVICE MANUAL

North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com

Asia/Oceania http://biz.lgservice.com

Internal Use Only

- 2 -

Only for training and service purposes

CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ........................................................................ 3

SERVICING PRECAUTIONS .................................................................... 4

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 14

BLOCK DIAGRAM ................................................................................. 21

EXPLODED VIEW .................................................................................. 22

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

- 3 -

Only for training and service purposes

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the

Schematic Diagram and Exploded View.

It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent

Shock, Fire, or other Hazards.

Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the

servicing of a receiver whose chassis is not isolated from the AC

power line. Use a transformer of adequate power rating as this

protects the technician from accidents resulting in personal injury

from electrical shocks.

It will also protect the receiver and it's components from being

damaged by accidental shorts of th e cir cuitry that may be

inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,

replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,

over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to

be sure the set is safe to operate without damage of electrical

shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an

electrical jumper across the two AC plug prongs. Place the AC

switch in the on position, connect one lead of ohm-meter to the AC

plug prongs tied together and touch other ohm-meter lead in turn to

each exposed metallic parts such as antenna terminals, phone

jacks, etc.

If the exposed metallic part has a return path to the chassis, the

measured resistance should be between 1 MΩ and 5.2 MΩ.

When the exposed metal has no return path to the chassis the

reading must be infinite.

An other abnormality exists that must be corrected before the

receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.

Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor

between a known good earth ground (Water Pipe, Conduit, etc.)

and the exposed metallic parts.

Measure the AC voltage across the resistor using AC voltmeter

with 1000 ohms/volt or more sensitivity.

Reverse plug the AC cord into the AC outlet and repeat AC voltage

measurements for each exp ose d metallic par t. Any voltage

measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA.

In case any measurement is out of the limits specified, there is

possibility of shock hazard and the set must be checked and

repaired before it is returned to the customer.

Leakage Current Hot Check circuit

IMPORTANT SAFETY NOTICE

SAFETY PRECAUTIONS

- 4 -

Only for training and service purposes

SERVICING PRECAUTIONS

CAUTION: Before servicing receivers covered by this service

manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication.

NOTE: If unforeseen circumstances create conict between the

following servicing precautions and any of the safety precautions

on page 3 of this publication, always follow the safety precau-

tions. Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power

source before;

a. Removing or reinstalling any component, circuit board

module or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug

or other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver.

CAUTION: A wrong part substitution or incorrect polarity

installation of electrolytic capacitors may result in an explo-

sion hazard.

2. Test high voltage only by measuring it with an appropriate

high voltage meter or other voltage measuring device (DVM,

FETVOM, etc) equipped with a suitable high voltage probe.

Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its

assemblies.

4. Unless specied otherwise in this service manual, clean

electrical contacts only by applying the following mixture to the

contacts with a pipe cleaner, cotton-tipped stick or comparable

non-abrasive applicator; 10 % (by volume) Acetone and 90 %

(by volume) isopropyl alcohol (90 % - 99 % strength)

CAUTION: This is a ammable mixture.

Unless specied otherwise in this service manual, lubrication

of contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which

receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its

electrical assemblies unless all solid-state device heat sinks

are correctly installed.

7. Always connect the test receiver ground lead to the receiver

chassis ground before connecting the test receiver positive

lead.

Always remove the test receiver ground lead last.

8. Use with this receiver only the test xtures specied in this

service manual.

CAUTION: Do not connect the test xture ground strap to any

heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged eas-

ily by static electricity. Such components commonly are called

Electrostatically Sensitive (ES) Devices. Examples of typical ES

devices are integrated circuits and some eld-effect transistors

and semiconductor “chip” components. The following techniques

should be used to help reduce the incidence of component dam-

age caused by static by static electricity.

1. Immediately before handling any semiconductor component or

semiconductor-equipped assembly, drain off any electrostatic

charge on your body by touching a known earth ground. Alter-

natively, obtain and wear a commercially available discharg-

ing wrist strap device, which should be removed to prevent

potential shock reasons prior to applying power to the unit

under test.

2. After removing an electrical assembly equipped with ES

devices, place the assembly on a conductive surface such as

aluminum foil, to prevent electrostatic charge buildup or expo-

sure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder

ES devices.

4. Use only an anti-static type solder removal device. Some sol-

der removal devices not classied as “anti-static” can generate

electrical charges sufcient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate

electrical charges sufcient to damage ES devices.

6. Do not remove a replacement ES device from its protective

package until immediately before you are ready to install it.

(Most replacement ES devices are packaged with leads elec-

trically shorted together by conductive foam, aluminum foil or

comparable conductive material).

7. Immediately before removing the protective material from the

leads of a replacement ES device, touch the protective mate-

rial to the chassis or circuit assembly into which the device will

be installed.

CAUTION: Be sure no power is applied to the chassis or cir-

cuit, and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged replace-

ment ES devices. (Otherwise harmless motion such as the

brushing together of your clothes fabric or the lifting of your

foot from a carpeted oor can generate static electricity suf-

cient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropri-

ate tip size and shape that will maintain tip temperature within

the range or 500 °F to 600 °F.

2. Use an appropriate gauge of RMA resin-core solder composed

of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wire-

bristle (0.5 inch, or 1.25 cm) brush with a metal handle.

Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique

a. Allow the soldering iron tip to reach normal temperature.

(500 °F to 600 °F)

b. Heat the component lead until the solder melts.

c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique.

a. Allow the soldering iron tip to reach a normal temperature

(500 °F to 600 °F)

b. First, hold the soldering iron tip and solder the strand

against the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there

only until the solder ows onto and around both the compo-

nent lead and the foil.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

- 5 -

Only for training and service purposes

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through

which the IC leads are inserted and then bent at against the cir-

cuit foil. When holes are the slotted type, the following technique

should be used to remove and replace the IC. When working with

boards using the familiar round hole, use the standard technique

as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by

gently prying up on the lead with the soldering iron tip as the

solder melts.

2. Draw away the melted solder with an anti-static suction-type

solder removal device (or with solder braid) before removing

the IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and

solder it.

3. Clean the soldered areas with a small wire-bristle brush.

(It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor

Removal/Replacement

1. Remove the defective transistor by clipping its leads as close

as possible to the component body.

2. Bend into a "U" shape the end of each of three leads remain-

ing on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding

leads extending from the circuit board and crimp the "U" with

long nose pliers to insure metal to metal contact then solder

each connection.

Power Output, Transistor Device

Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit

board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as pos-

sible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit

board.

3. Observing diode polarity, wrap each lead of the new diode

around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of

the two "original" leads. If they are not shiny, reheat them and

if necessary, apply additional solder.

Fuse and Conventional Resistor

Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow

stake.

2. Securely crimp the leads of replacement component around

notch at stake top.

3. Solder the connections.

CAUTION: Maintain original spacing between the replaced

component and adjacent components and the circuit board to

prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit

board will weaken the adhesive that bonds the foil to the circuit

board causing the foil to separate from or "lift-off" the board. The

following guidelines and procedures should be followed when-

ever this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the

following procedure to install a jumper wire on the copper pattern

side of the circuit board. (Use this technique only on IC connec-

tions).

1. Carefully remove the damaged copper pattern with a sharp

knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if

used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and

carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper

pattern and let it overlap the previously scraped end of the

good copper pattern. Solder the overlapped area and clip off

any excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern

at connections other than IC Pins. This technique involves the

installation of a jumper wire on the component side of the circuit

board.

1. Remove the defective copper pattern with a sharp knife.

Remove at least 1/4 inch of copper, to ensure that a hazardous

condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern

break and locate the nearest component that is directly con-

nected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the

nearest component on one side of the pattern break to the

lead of the nearest component on the other side.

Carefully crimp and solder the connections.

CAUTION: Be sure the insulated jumper wire is dressed so the

it does not touch components or sharp edges.

- 6 -

Only for training and service purposes

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

1. Application range

This specification is applied to the LED TV used LD33B

chassis.

2. Requirement for Test

Each part is tested as below without special appointment.

1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage

: Standard input voltage (AC 100-240 V~, 50/60 Hz)

* Standard Voltage of each products is marked by models.

4) Specification and performance of each parts are followed

ea ch drawing and s pe cificatio n b y p art number in

accordance with BOM.

5) The receiver must be operated for about 20 minutes prior to

the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : CE, IEC specification

- EMC : CE, IEC

4. Model General Specification

No. Item Specication Remarks

1 Market EU(PAL Market-37Countries) DTV & Analog (Total 37 countries)

DTV (MPEG2/4, DVB-T) : 29 countries

Germany, Netherland, Switzerland, Hungary, Austria, Slov-

enia, Bulgaria, France, Spain, Italy, Belgium, Luxemburg,

Greece, Czech, Croatia, Turkey, Moroco, Ireland, Latvia,

Estonia, Lithuania, Poland, Portugal, Romania, Albania,

Bosnia, Serbia, Slovakia, Beralus

DTV (MPEG2/4, DVB-T2): 8 countries

UK(Ireland), Sweden, Denmark, Finland, Norway, Ukraine,

Kazakhstan, Russia

DTV (MPEG2/4, DVB-C): 37 countries

Germany, Netherland, Switzerland, Hungary, Austria,

Slovenia, Bulgaria, France, Spain, Italy, Belgium, Russia,

Luxemburg, Greece, Czech, Croatia, Turkey, Moroco, Ire-

land, Latvia, Estonia, Lithuania, Poland, Portugal, Romania,

Albania, Bosnia, Serbia, Slovakia, Beralus, UK, Sweden,

Denmark, Finland, Norway, Ukraine, Kazakhstan

DTV (MPEG2/4,DVB-S): 30 countries

Germany, Netherland, Switzerland, Hungary, Austria,

Slovenia, Bulgaria, France, Spain, Italy, Belgium, Russia,

Luxemburg, Greece, Czech, Croatia, Turkey, Moroco, Ire-

land, Latvia, Estonia, Lithuania, Poland, Portugal, Romania,

Albania, Bosnia, Serbia, Slovakia, Beralus

Supported satellite : 22 satellites

HISPASAT 1C/1D, ATLANTIC BIRD 2, NILESAT 101/102,

ATLANTIC BIRD 3, AMOS 2/3, THOR 5/6, IRIUS 4,

EUTELSAT-W3A, EUROBIRD 9A, EUTELSAT-W2A,

HOTBIRD 6/8/9, EUTELSAT-SESAT, ASTRA 1L/H/M/

KR, ASTRA 3A/3B, BADR 4/6, ASTRA 2D, EUROBIRD 3,

EUTELSAT-W7, HELLASSAT 2, EXPRESS AM1, TURK-

SAT 2A/3A, INTERSAT10

- 7 -

Only for training and service purposes

No. Item Specication Remarks

2 Broadcasting system

1) PAL-BG

2) PAL-DK

3) PAL-I/I’

4) SECAM-L/L', DK , BG, I

5) DVB-T

6) DVB-C

7) DVB-T2

8) DVB-S/S2

Model : *L*V*-Z* (T2 only Model)

DVB-S: Satellite

3 Program coverage

1 ) Digital TV

- VHF, UHF

- C-Band,Ku-Band

2) Analogue TV

- VHF : E2 to E12

- UHF : E21 to E69

- CATV : S1 to S20

- HYPER : S21 to S47

4 Receiving system

Analog : Upper Heterodyne

Digital : COFDM, QAM

► DVB-T

- Guard Interval(Bitrate_Mbit/s)

1/4, 1/8, 1/16, 1/32

- Modulation : Code Rate

QPSK : 1/2, 2/3, 3/4, 5/6, 7/8

16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8

64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8

► DVB-T2 (Model : *L*V*-Z* (T2 only Model))

- Guard Interval(Bitrate_Mbit/s)

1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,

- Modulation : Code Rate

QPSK : 1/2, 2/5, 2/3, 3/4, 5/6

16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6

64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6

256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6

► DVB-C

- Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s

- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM

► DVB-S/S2

- symbolrate

DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s

DVB-S (QPSK) : 2 ~ 45Msymbol/s

- viterbi

DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8

DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10

5 Scart (1EA) PAL, SECAM

Scart 1 Jack is Full scart and support ATV/DTV-OUT

(not support DTV Auto AV)

6 Video Input RCA(1EA) PAL, SECAM, NTSC

4 System : PAL, SECAM, NTSC, PAL60

Common port

7 Head phone out

Antenna, AV1, AV2, Component, HDMI1,

HDMI2, HDMI3, USB1, USB2, USB3

8 Component Input (1EA)

Y/Cb/Cr

Y/Pb/Pr

Hybrid Type

9 HDMI Input (3EA)

HDMI1-DTV

HDMI2-DTV

HDMI3-DTV

HDMI1: PC support(HDMI version 1.3)

Support HDCP

10 Audio Input (3EA)

DVI Audio

Component/AV2

AV1

L/R Input.

11 SDPIF out (1EA) SPDIF out

12 USB (1EA) EMF, DivX HD, For SVC (download) JPEG, MP3, DivX HD

13 Ethernet Connect(1EA) Ethernet Connect

- 8 -

Only for training and service purposes

5. Component Video Input (Y, Pb, Pr)

No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock

1. 720×480 15.73 60.00 SDTV, DVD 480i

2. 720×480 15.63 59.94 SDTV, DVD 480i

3. 720×480 31.47 59.94 480p

4. 720×480 31.50 60.00 480p

5. 720×576 15.625 50.00 SDTV 576i

6. 720×576 31.25 50.00 SDTV 576p

7. 1280×720 45.00 50.00 HDTV 720p

8. 1280×720 44.96 59.94 HDTV 720p

9. 1280×720 45.00 60.00 HDTV 720p

10. 1920×1080 31.25 50.00 HDTV 1080i

11. 1920×1080 33.75 60.00 HDTV 1080i

12. 1920×1080 33.72 59.94 HDTV 1080i

13. 1920×1080 56.250 50 HDTV 1080p

14. 1920×1080 67.5 60 HDTV 1080p

- 9 -

Only for training and service purposes

6.2. PC mode

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz)

1 640 x 350 @70Hz 31.468 70.09 EGA

2 720 x 400 @70Hz 31.469 70.08 DOS

3 640 x 480 @60Hz 31.469 59.94 VESA(VGA)

4 800 x 600 @60Hz 37.879 60.31 VESA(SVGA)

5 1024 x 768 @60Hz 48.363 60.00 VESA(XGA)

6 1152 x 864 @60Hz 54.348 60.053 VESA

7 1280 x 1024 @60Hz 63.981 60.020 VESA(SXGA)

8 1360 x 768 @60Hz 47.712 60.015 VESA(WXGA)

9 1920 x 1080 @60Hz 67.5 60.00 WUXGA(Reduced Blanking)

10. 1920*1080 25 HDTV 1080P

11. 1920*1080 33.716 / 33.75 29.976 / 30.00 HDTV 1080P

12. 1920*1080 56.250 50 HDTV 1080P

13. 1920*1080 67.43 / 67.5 59.94 / 60 HDTV 1080P

6. HDMI Input

6.1. DTV mode

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz)

1. 640*480 31.469 / 31.5 59.94/60 SDTV 480P

2. 720*480 31.469 / 31.5 59.94 / 60 SDTV 480P

3. 720*576 31.25 50 SDTV 576P

4. 720*576 15.625 50 SDTV 576I

5. 1280*720 37.500 50 HDTV 720P

6. 1280*720 44.96 / 45 59.94 / 60 HDTV 720P

7. 1920*1080 33.72 / 33.75 59.94 / 60 HDTV 1080I

8. 1920*1080 28.125 50.00 HDTV 1080I

9. 1920*1080 26.97 / 27 23.97 / 24 HDTV 1080P

10. 1920*1080 25 HDTV 1080P

11. 1920*1080 33.716 / 33.75 29.976 / 30.00 HDTV 1080P

12. 1920*1080 56.250 50 HDTV 1080P

13. 1920*1080 67.43 / 67.5 59.94 / 60 HDTV 1080P

- 10 -

Only for training and service purposes

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC 3D input proposed mode Proposed

640*480

31.469 / 31.5 59.94/ 60 25.125 1

Top-and-Bottom

Side-by-side(half)

Secondary(SDTV 480P)

2 62.938/63 59.94/ 60 50.35/50.4 1

Frame packing

Line alternative

Secondary(SDTV 480P)

(SDTV 480P)

3 31.469 / 31.5 59.94/ 60 50.35/50.4 1 Side-by-side(Full) (SDTV 480P)

720*480

31.469 / 31.5 59.94 / 60 27.00/27.03 2,3

Top-and-Bottom

Side-by-side(half)

Secondary(SDTV 480P)

5 62.938/63 59.94 / 60 54/54.06 2,3

Frame packing

Line alternative

Secondary(SDTV 480P)

(SDTV 480P)

6 31.469 / 31.5 59.94 / 60 54/54.06 2,3 Side-by-side(Full) (SDTV 480P)

720*576

31.25 50 27 17,18

Top-and-Bottom

Side-by-side(half)

Secondary(SDTV 576P)

8 62.5 50 54 17,18

Frame packing

Line alternative

Secondary(SDTV 576P)

(SDTV 576P)

9 31.25 50 54 17,18 Side-by-side(Full) (SDTV 576P)

720*576

15.625 50 27 21

Top-and-Bottom

Side-by-side(half)

Secondary(SDTV 576I)

11 31.25 50 54 21

Frame packing

Field alternative

Secondary(SDTV 576I)

(SDTV 576I)

12 15.625 50 54 21 Side-by-side(Full) (SDTV 576I)

1280*720

37.500 50 74.25 19

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 720P)

14 75 50 148.5 19

Frame packing

Line alternative

Primary(HDTV 720P)

(HDTV 720P)

15 37.500 50 148.5 19 Side-by-side(Full) (HDTV 720P)

16 44.96 / 45 59.94 / 60 74.18/74.25 4

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 720P)

17 89.91/90 59.94 / 60 148.35/148.5 4

Frame packing

Line alternative

Primary(HDTV 720P)

(HDTV 720P)

18 44.96 / 45 59.94 / 60 148.35/148.5 4 Side-by-side(Full) (HDTV 720P)

1920*1080

33.72 / 33.75 59.94 / 60 74.18/74.25 5

Top-and-Bottom

Side-by-side(half)

Secondary(HDTV 1080I)

Primary(HDTV 1080I)

20 67.432 / 67.50 59.94 / 60 148.35/148.5 5

Frame packing

Field alternative

Primary(HDTV 1080I)

(HDTV 1080I)

21 33.72 / 33.75 59.94 / 60 148.35/148.5 5 Side-by-side(Full) (HDTV 1080I)

22 28.125 50.00 74.25 20

Top-and-Bottom

Side-by-side(half)

Secondary(HDTV 1080I)

Primary(HDTV 1080I)

23 56.25 50.00 148.5 20

Frame packing

Field alternative

Primary(HDTV 1080I)

(HDTV 1080I)

24 28.125 50.00 148.5 20 Side-by-side(Full) (HDTV 1080I)

1920*1080

26.97 / 27 23.97 / 24 74.18/74.25 32

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 1080P)

26 43.94/54 23.97 / 24 148.35/148.5 32

Frame packing

Line alternative

Primary(HDTV 1080P)

(HDTV 1080P)

27 26.97 / 27 23.97 / 24 148.35/148.5 32 Side-by-side(Full) (HDTV 1080P)

28 28.125 25 74.25 33

Top-and-Bottom

Side-by-side(half)

Secondary(HDTV 1080P)

29 56.24 25 148.5 33

Frame packing

Line alternative

Secondary(HDTV 1080P)

(HDTV 1080P)

30 28.12 25 148.5 33 Side-by-side(Full) (HDTV 1080P)

31 33.716 / 33.75 29.976 / 30.00 74.18/74.25 34

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 1080P)

Secondary(HDTV 1080P)

32 67.432 / 67.5 29.976 / 30.00 148.35/148.5 34

Frame packing

Line alternative

Primary(HDTV 1080P)

(HDTV 1080P)

33 33.716 / 33.75 29.976 / 30.00 148.35/148.5 34 Side-by-side(Full) (HDTV 1080P)

34 56.250 50 148.5 31

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 1080P)

Secondary(HDTV 1080P)

35 67.43 / 67.5 59.94 / 60 148.35/148.50 16

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 1080P)

Secondary(HDTV 1080P)

7. 3D Mode

7.1. HDMI 1.4b (3D supported mode automatically)

- 11 -

Only for training and service purposes

7.3. RF Input(3D supported mode manually)

No. Resolution Proposed 3D input proposed mode

1 HD

1080I

720P

2D to 3D

Side by Side(Half)

Top & Bottom

2 SD

576P

576I

2D to 3D

7.4. RF Input (3D supported mode automatically)

No. Signal 3D input proposed mode

1 Frame Compatible

Side by Side(Half),

Top & Bottom

7.2. HDMI Input(1.3)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode

1 1280*720 45.00 60.00 74.25 HDTV 720P

2D to 3D, Side by Side(half),

Top & Bottom, Single Frame Sequential

2 1280*720 37.500 50 74.25 HDTV 720P

3 1920*1080 33.75 60.00 74.25 HDTV 1080I

2D to 3D, Side by Side(half),

Top & Bottom

4 1920*1080 28.125 50.00 74.25 HDTV 1080I

5 1920*1080 27.00 24.00 74.25 HDTV 1080P

2D to 3D, Side by Side(Half),

Top & Bottom, Checker Board

6 1920*1080 28.12 25 74.25 HDTV 1080P

7 1920*1080 33.75 30.00 74.25 HDTV 1080P

8 1920*1080 67.50 60.00 148.5 HDTV 1080P

2D to 3D, Side by Side(half),

Top & Bottom, Checkerboard,

Single Frame Sequential,

Row Interleaving, Column Interleaving

9 1920*1080 56.25 50 148.5 HDTV 1080P

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode

1 1920*1080 33.75 30 74.25 HDTV 1080P

2D to 3D, Side by Side(Half)*,

Top & Bottom*, Checkerboard*,

Row Interleaving, Column Interleaving

(Photo : side by Side(half), Top & Bottom)

Others - - -

640*350

720*400

640*480

800*600

1152*864

1280*1024

2D to 3D

7.5. USB Input (3D supported mode manually)

(“*” 3D supported mode manually & automatically)

- 12 -

Only for training and service purposes

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Proposed 3D input proposed mode

1 1280*720 45.00 60.00 74.25 HDTV 720P

2D to 3D, Side by Side(Half), Top & Bottom

2 1280*720 37.500 50 74.25 HDTV 720P

3 1920*1080 33.75 60.00 74.25 HDTV 1080I

4 1920*1080 28.125 50.00 74.25 HDTV 1080I

5 1920*1080 27.00 24.00 74.25 HDTV 1080P

6 1920*1080 28.12 25 74.25 HDTV 1080P

7 1920*1080 33.75 30.00 74.25 HDTV 1080P

8 1920*1080 67.50 60.00 148.5 HDTV 1080P

9 1920*1080 56.250 50 148.5 HDTV 1080P

7.8. Component Input(3D) (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

1 1024*768 48.36 60 65

2D to 3D, Side by Side(half)

Top & Bottom

HDTV 768P

2 1360*768 47.71 60 85.5

2D to 3D, Side by Side(half)

Top & Bottom

HDTV 768P

3 1920*1080 67.500 60 148.50

2D to 3D, Side by Side(half)

Top & Bottom, Checker Board,

Single Frame Sequential,

Row Interleaving,

Column Interleaving

HDTV 1080P

4 Others - - - 2D to 3D

640*350

720*400

640*480

800*600

1152*864

7.6. HDMI-PC Input (3D supported mode manually)

7.7. DLNA Input (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode

1 1920*1080 33.75 30 74.25

2D to 3D, Side by Side(Half)*,Top &

Bottom*,Checker Board*, Row Interleav-

ing, Column Interleaving(Photo : Side by

Side(Half), Top&Bottom)

7.9. 3D Input mode

No. Side by Side Top & Bottom Checker board

Single Frame

Sequential

Frame

Packing

2D to 3D

ii.

iii.

iv.

vi.

(“*” 3D supported mode manually & automatically)

- 13 -

Only for training and service purposes

ADJUSTMENT INSTRUCTION

1. Application Range

This specification sheet is applied to all of the LED TV with

LD33B chassis.

2. Designation

(1) Because this is not a hot chassis, it is not necessary to

use an isolation transformer. However, the use of isolation

transformer will help protect test instrument.

(2) Adjustment must be done in the correct order.

(3) The adjustment must be performed in the circumstance of

25 °C ± 5 °C of temperature and 65 % ± 10 % of relative

humidity if there is no specific designation.

(4) The input voltage of the receiver must keep AC 100-240

V~, 50/60 Hz.

(5) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15.

In case of keeping module is in the circumstance of 0 °C, it

should be placed in the circumstance of above 15 °C for 2

hours.

In case of keeping module is in the circumstance of below

-20 °C, it should be placed in the circumstance of above 15

°C for 3 hours.

[Caution]

When still image is displayed for a period of 20 minutes or

longer (Especially where W/B scale is strong. Digital pattern

13ch and/or Cross hatch pattern 09ch), there can some

afterimage in the black level area.

3. Automatic Adjustment

3.1. MAC address D/L, CI+ key D/L, Widevine

key D/L, ESN D/L, HDCP14/20 D/L

Connect: USB port

Communication Prot connection

▪ Com 1,2,3,4 and 115200(Baudrate)

Mode check: Online Only

▪ Check the test process: DETECT -> MAC -> CI -> Widevine

-> ESN -> HDCP14 -> HDCP20

▪ Play: Press Enter key

▪ Result: Ready, Test, OK or NG

▪ Printer Out (MAC Address Label)

3.2. LAN Inspection

3.2.1. Equipment & Condition

▪ Each other connection to LAN Port of IP Hub and Jig

3.2.2. LAN inspection solution

▪ LAN Port connection with PCB

▪ Setting automatic IP

▪ If you want manual connection, enter Network connection at

MENU Mode of TV. Press Start connection key, then

Network will be connected.

▪ Setting state confirmation

- If automatic setting is finished, you confirm IP and MAC

Address at ‘in start’ menu mode.



- 14 -

Only for training and service purposes

3.2.3. WIDEVINE key Inspection

- Confirm key input data at the "IN START" MENU Mode.

3.3. LAN PORT INSPECTION(PING TEST)

Connect SET → LAN port == PC → LAN Port

3.3.1. Equipment setting

(1) Play the LAN Port Test PROGRAM.

(2) Input IP set up for an inspection to Test Program.

*IP Number : 12.12.2.2

3.3.2. LAN PORT inspection(PING TEST)

(1) Play the LAN Port Test Program.

(2) Connect each other LAN Port Jack.

(3) Play Test (F9) button and confirm OK Message.

(4) Remove LAN cable.

3.4. Model name & Serial number Download

3.4.1. Model name & Serial number D/L

▪ Press "P-ONLY" key of service remote control.

(Baud rate : 115200 bps)

▪ Connect RS-232C Signal to USB Cable to USB.

▪ Write Serial number by use USB port.

▪ Must check the serial number at Instart menu.

3.4.2. Method & notice

(1) Serial number D/L is using of scan equipment.

(2) Setting of scan equipment operated by Manufacturing

Technology Group.

(3) Serial number D/L must be conformed when it is produced

in production line, because serial number D/L is mandatory

by D-book 4.0.

* Manual Download (Model Name and Serial Number)

If the TV set is downloaded by OTA or service man, sometimes

model name or serial number is initialized.(Not always)

It is impossible to download by bar code scan, so It need

Manual download.

1) Press the "Instart" key of Adjustment remote control.

2) Go to the menu "7.Model Number D/L" like below photo.

3) Input the Factory model name(ex 42LA690V-ZA) or Serial

number like photo.

4) Check the model name Instart menu. → Factory name

displayed. (ex 42LA690V-ZA)

5) Check the Diagnost ics.(DTV country only) → Buyer

model displayed. (ex 42LA690V-ZA)

3.5. CI+ Key checking method

- Check the Section 3.1

Check whether the key was downloaded or not at ‘In Start’

menu. (Refer to below).

=> Check the Download to CI+ Key value in LGset.



SET PC

- 15 -

Only for training and service purposes

3.5.1. Check the method of CI+ Key value

(1) Check the method on Instart menu

(2) Check the method of RS232C Command

1) Into the main ass’y mode(RS232: aa 00 00)

2) Check the key download for transmitted command

(RS232: ci 00 10)

3) Result value

- Normally status for download : OKx

- Abnormally status for download : NGx

3.5.2. Check the method of CI+ key value(RS232)

1) Into the main ass’y mode(RS232: aa 00 00)

2) Check the mothed of CI+ key by command

(RS232: ci 00 20)

3) Result value

i 01 OK 1d1852d21c1ed5dcx

3.6. WIFI MAC ADDRESS CHECK

(1) Using RS232 Command

(2) Check the menu on in-start

4. Manual Adjustment

* ADC adjustment is not needed because of OTP(Auto ADC

adjustment)

4.1. EDID DATA

4.1.1. 3D EDID

▪ Reference

- HDMI1 ~ HDMI4 / RGB

- In the data of EDID, bellows may be different by S/W or

Input mode.

ⓐ Product ID

ⓑ Serial No: Controlled on production line.

ex) Monthly : ‘01’ → ‘01’

Year : ‘2013’ → ‘17’

ⓓ Model Name(Hex): LGTV

ⓔ Checksum(LG TV): Changeable by total EDID data.

ⓕ Vendor Specific(HDMI)

1) Deep color (module 10bit)

2) None deep color (module 8bit)

ⓖ Colorimetry Data Block(HDMI)

1) The Model not supporting XvYcc

H-freq(kHz) V-freq.(Hz)

Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]

CMD 1 CMD 2 Data 0

A A 0 0

CMD 1 CMD 2 Data 0

C I 1 0

CMD 1 CMD 2 Data 0

A A 0 0

CMD 1 CMD 2 Data 0

C I 2 0

CI+ Key Value

HEX EDID Table DDC Function

0001 0100 Analog

0001 0100 Digital

Chassis MODEL NAME(HEX)

LD33B 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20

ⓔ1 ⓔ2 ⓔ2 ⓔ3

10bit

/none XvYcc

8bit

/none XvYcc

HDMI1 E8 85 CC X

HDMI2 E8 75 BC X

HDMI3 E8 65 AC X

INPUT MODEL NAME(HEX)

HDMI1 78 03 0C 00 10 00 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

HDMI2 78 03 0C 00 20 00 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

HDMI3 78 03 0C 00 30 00 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

INPUT MODEL NAME(HEX)

HDMI1 E3 05 00 00

HDMI2 E3 05 00 00

HDMI3 E3 05 00 00

INPUT MODEL NAME(HEX)

HDMI1 78 03 0C 00 10 00 80 1E 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

HDMI2 78 03 0C 00 20 00 80 1E 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

HDMI3 78 03 0C 00 30 00 80 1E 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

- 16 -

Only for training and service purposes

4.1.2. 2D EDID

▪ Reference

- HDMI1 ~ HDMI4 / RGB

- In the data of EDID, bellows may be different by S/W or

Input mode.

ⓐ Product ID

ⓑ Serial No: Controlled on production line.

ex) Monthly : ‘01’ → ‘01’

Year : ‘2012’ → ‘16’

ⓓ Model Name(Hex): LGTV

ⓔ Checksum(LG TV): Changeable by total EDID data.

ⓕ Vendor Specific(HDMI)

4.2. White Balance Adjustment

4.2.1. Overview

▪ W/B adj. Objective & How-it-works

(1) Objective: To reduce each Panel's W/B deviation

(2) How-it-works : When R/G/B gain in the OSD is at 192, it

means the panel is at its Full Dynamic Range. In order to

prevent saturation of Full Dynamic range and data, one

of R/G/B is fixed at 192, and the other two is lowered to

find the desired value.

(3) Adjustment condition : normal temperature

1) Surrounding Temperature : 25 °C ± 5 °C

2) Surrounding Humidity : 20 % ~ 80 %

4.2.2. Equipment

(1) Color Analyzer: CA-210 (LED Module : CH 14)

(2) Adjustment Computer(During auto adj., RS-232C protocol

is needed)

(3) Adjustment Remote control

(4) Video Signal Generator MSPG-925F 720p/216-Gray

(Model: 217, Pattern: 78)

→ Only when internal pattern is not available

▪ Color Analyzer Matrix should be calibrated using CS-1000.

4.2.3. Equipment connection MAP

4.2.4. Adj. Command (Protocol)

- LEN: Number of Data Byte to be sent

- CMD: Command

- VAL: FOS Data value

- CS: Checksum of sent data

- A: Acknowledge

Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]

▪ RS-232C Command used during auto-adjustment.

Ex) wb 00 00 -> Begin white balance auto-adj.

wb 00 10 -> Gain adj.

ja 00 ff -> Adj. data

jb 00 c0

...

wb 00 1f → Gain adj. completed

*(wb 00 20(Start), wb 00 2f(end)) → Off-set adj.

wb 00 ff → End white balance auto-adj.

▪ Adj. Map

Applied Model : LD33B Chassis ALL MODELS

HEX EDID Table DDC Function

0001 0100 Analog

0001 0100 Digital

Chassis MODEL NAME(HEX)

LD33B 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20

ⓔ1 ⓔ2 ⓔ3

HDMI1 43 15 X

HDMI2 43 05 X

HDMI3 43 F5 X

INPUT MODEL NAME(HEX)

HDMI1 67 03 0C 00 10 00 80 2D

HDMI2 67 03 0C 00 20 00 80 2D

HDMI3 67 03 0C 00 30 00 80 2D

START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP

Co lor Anal yze r

Co mp ute r

Pattern Gen era to r

RS -232 C

RS- 232 C

Pro be

Sig nal Sou rce

* If TV internal pattern is used, not needed

RS-232C COMMAND

[CMD ID DATA]

Explantion

wb 00 00 Begin White Balance adjustment

wb 00 10 Gain adjustment(internal white pattern)

wb 00 1f Gain adjustment completed

wb 00 20 Offset adjustment(internal white pattern)

wb 00 2f Offset adjustment completed

wb 00 ff

End White Balance adjustment

(internal pattern disappears )

Adj. item

Command

(lower caseASCII)

Data Range

(Hex.)

Default

(Decimal)

CMD1 CMD2 MIN MAX

Cool

R Gain j g 00 C0

G Gain j h 00 C0

B Gain j i 00 C0

R Cut

G Cut

B Cut

Medium

R Gain j a 00 C0

G Gain j b 00 C0

B Gain j c 00 C0

R Cut

G Cut

B Cut

Warm

R Gain j d 00 C0

G Gain j e 00 C0

B Gain j f 00 C0

R Cut

G Cut

- 17 -

Only for training and service purposes

4.2.5. Adj. method

(1) Auto adj. method

1) Set TV in adj. mode using POWER ON key.

2) Zero calibrate probe then place it on the center of the

Display.

3) Connect Cable.(RS-232C to USB)

4) Select mode in adj. Program and begin adj.

5) When adj. is complete (OK Sign), check adj. status pre

mode. (Warm, Medium, Cool)

6) Remove probe and RS-232C cable to complete adj.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need.

(2) Manual adjustment. method

1) Set TV in Adj. mode using POWER ON.

2) Zero Calibrate the probe of Color Analyzer, then place it

on the center of LCD module within 10 cm of the

surface.

3) Press ADJ key → EZ adjust using adj. R/C → 7. White-

Balance then press the cursor to the right(key ►).

(When right key(►) is pressed 204 Gray internal pattern

will be displayed)

4) One of R Gain / G Gain / B Gain should be fixed at 192,

and the rest will be lowered to meet the desired value.

5) Adjustment is performed in COOL, MEDIUM, WARM 3

modes of color temperature.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 7.White Balance, you can select one of 2 Test-

pattern: ON, OFF. Default is inner(ON). By selecting OFF,

you can adjust using RF signal in 204 Gray pattern.

▪ Adjustment condition and cautionary items

1) Lighting condition in surrounding area

Surrounding lighting should be lower 10 lux. Try to

isolate adj. area into dark surrounding.

2) Probe location

: Color Analyzer(CA-210) probe should be within 10 cm

and perpendicular of the module surface (80° ~ 100°)

3) Aging time

- After Aging Start, Keep the Power ON status during 5

Minutes.

- In case of LCD, Back-light on should be checked

using no signal or Full-white pattern.

4.2.6. Reference (White balance Adj. coordinate and

color temperature)

▪ Luminance : 204 Gray

▪ Standard color coordinate and temperature using CS-1000

(over 26 inch)

▪ Standard color coordinate and temperature using CA-210(CH 14)

4.2.7. ALELF & EDGE LED White balance table

- EDGE LED module change color coordinate because of

aging time.

- Apply under the color coordinate table, for compensated

aging time.

* Normal Line

[LN5xxx, LA6xxx, LA7xxx, LA8xxx]

*Aging Chamber

[LN5xxx, LA6xxx, LA7xxx, LA8xxx]

Mode

Coordinate

Temp ∆uv

x y

Cool 0.269 0.273 13000 K 0.0000

Medium 0.285 0.293 9300 K 0.0000

Warm 0.313 0.329 6500 K 0.0000

Mode

Coordinate

Temp ∆uv

x y

Cool 0.269 ± 0.002 0.273 ± 0.002 13000 K 0.0000

Medium 0.285 ± 0.002 0.293 ± 0.002 9300 K 0.0000

Warm 0.313 ± 0.002 0.329 ± 0.002 6500K 0.0000

NC4.0

Aging

time

(Min)

Cool Medium Warm

X y x y x y

271 270 286 289 313 329

1 0-2 283 287 298 306 322 342

2 3-5 282 285 297 304 321 340

3 6-9 281 284 296 303 320 339

4 10-19 279 281 294 300 318 336

5 20-35 277 277 292 296 316 332

6 36-49 275 274 290 293 314 329

7 50-79 273 272 288 291 312 327

8 80-119 272 271 287 290 311 326

9 Over 120 271 270 286 289 310 325

NC4.0

Aging

time

(Min)

Cool Medium Warm

X y x y x y

271 270 286 289 313 329

1 0-5 282 285 297 304 321 340

2 6-10 278 280 293 299 317 335

3 11-20 275 275 290 294 314 330

4 21-30 272 272 287 291 311 327

5 31-40 269 269 284 288 308 324

6 41-50 268 267 283 286 307 322

7 51-80 267 266 282 285 306 321

8 81-119 266 264 281 283 305 319

9 Over 120 265 263 280 282 304 318

- 18 -

Only for training and service purposes

4.3. Local Dimming Function Check

Step 1) Turn on TV.

Step 2) At the Local Dimming mode, module Edge Backlight

moving right to left Back light of IOP module moving.

Step 3) Confirm the Local Dimming mode.

Step 4) Press "exit" key.

4.4. Magic Motion Remote control test

- Re sults are automatically marked in In start OSD after

through the AP/Magic Remocon Equipment on the line

4.5. 3D function test

(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4])

* HDMI mode NO. 872 , pattern No.83

(1) Please input 3D test pattern like below.

(2) When 3D OSD appear automatically, then select OK key.

(3) Don't wear a 3D Glasses, check the picture like below.

4.6. Wi-Fi Test

Step 1) Turn on TV

Step 2) Select Network Connection option in Network Menu.

Step 3) Select Start Connection button in Network Connection.

Step 4) If the system finds any AP like blow PIC, it is working

well.

- 19 -

Only for training and service purposes

4.7. LNB voltage and 22KHz tone check

(only for DVB-S/S2 model)

▪ Test method

(1) Set TV in Adj. mode using POWER ON.

(2) Connect cable between satellite ANT and test JIG.

(3) Press Yellow key(ETC+SWAP) in Adj Remote control to

make LNB on.

(4) Check LED light ‘ON’ at 18 V menu.

(5) Check LED light ‘ON’ at 22 KHz tone menu.

(6) Press Blue key(ETC+PIP INPUT) in Adj Remote control

to make LNB off.

(7) Check LED light ‘OFF’ at 18 V menu.

(8) Check LED light ‘OFF’ at 22 KHz tone menu.

▪ Test result

(1) After press LNB On key, ‘18 V LED’ and ‘22 KHz tone

LED’ should be ON.

(2) After press LNB OFF key, ‘18 V LED’ and ‘22 KHz tone

LED’ should be OFF.

4.8. Option selection per country

4.8.1. Overview

- Option selection is only done for models in Non-EU

4.8.2. Method

(1) Press ADJ key on the Adj. R/C, then select Country Group

Meun

(2) Depending on destination, select Country Group Code 04

or Country Group EU then on the lower Country option,

select US, CA, MX. Selection is done using +, - or ►◄

key.

5. Tool Option selection

▪ Method : Press "ADJ" key on the Adjustment remote control,

then select Tool option.

6. Ship-out mode check(In-stop)

▪ After final inspection, press "IN-STOP" key of the Adjustment

remote control and check that the unit goes to Stand-by

mode.

7. GND and Internal Pressure check

7.1. Method

(1) GND & Internal Pressure auto-check preparation

- Check that Power cord is fully inserted to the SET.

(If loose, re-insert)

(2) Perform GND & Internal Pressure auto-check

- Unit fully inserted Power cord, Antenna cable and A/V

arrive to the auto-check process.

- Connect D-terminal to AV JACK TESTER

- Auto CONTROLLER(GWS103-4) ON

- Perform GND TEST

- If NG, Buzzer will sound to inform the operator.

- If OK, changeover to I/P check automatically.

(Remove CORD, A/V form AV JACK BOX.)

- Perform I/P test

- If NG, Buzzer will sound to inform the operator.

- If OK, Good lamp will lit up and the stopper will allow the

pallet to move on to next process.

7.2. Checkpoint

▪ TEST voltage

- GND: 1.5 KV / min at 100 mA

- SIGNAL: 3 KV / min at 100 mA

▪ TEST time: 1 second

▪ TEST POINT

- GND TEST = POWER CORD GND & SIGNAL CABLE

METAL GND

- Internal Pressure TEST = POWER CORD GND & LIVE &

NEUTRAL

▪ LEAKAGE CURRENT: At 0.5 mArms

8. Audio

Measurement condition:

(1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation

(2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms

(3) RGB PC: 1 KHz sine wave signal 0.7 Vrms

No. Item Min Typ Max Unit Remark

Audio practical

max Output, L/R

(Distortion=10%

max Output)

9 10 12 W

EQ Off

AVL Off

Clear Voice Off

8.10 10.8 Vrms

Speaker (8Ω

Impedance)

9 10 12 W

- 20 -

Only for training and service purposes

9. USB S/W Download(Service only)

(1) Put the USB Stick to the USB socket

(2) Automatically detecting update file in USB Stick

- If your downloaded program version in USB Stick is

Lower, it didn’t work.

But your downloaded version is Higher, USB data is

automatically detecting (Download Version High & Power

only mode, Set is automatically Download)

(3) Show the message “Do not unplug!”

(4) Updating is starting.

(5) Updating Completed, The TV will restart automatically

(6) If your TV is turned on, check your updated version and

Tool option. (explain the Tool option, next stage)

* If downloading version is more high than your TV have,

TV can lost all channel data. In this case, you have to

channel recover. if all channel data is cleared, you didn’t

have a DTV/ATV test on production line.

* After downloading, have to adjust Tool Option again.

(1) Push "IN-START" key in service remote control.

(2) Select "Tool Option 1" and push "OK" key.

(3) Punch in the number. (Each model has their number)

- 21 -

Only for training and service purposes

Audio AMP

LGE2122

CI Slot

P_TS

T/C Demod

IF (+/-)

USB1

OPTIC

LAN

DDR3

HDMI1

HDMI2

HDMI3

(MHL)

Analog Demod

SYSTEM EEPROM

HDMI

MUX

Air/

Cable

DVB-S

LNB

USB2

USB3

eMMC

Sub Micom

DDR3

P_TS

50P

X_TAL

T/C/S2 Tuner

A B

X_TAL

EPI

USB

P_TS

H/P

AV/COMP

SCART

OCP

(HDD)

MHL

(H)

AMP

CVBS/YPbPr

CVBS/RGB

SPDIF OUT

ETHERNET

LOCAL DIMMING

BLUTOOTH

LEVEL

SHIFTER

WIFI

KEY

LOGO LIGHT

SUB

ASSY

UART

USB_WIFI

OCP

SPI

BLOCK DIAGRAM

- 22 -

Only for training and service purposes

A10

AG1

900

200

400

540

521

530

910

120

122

570

123

502

500

501

510

LV1

* Set + Stand

* Stand Base + Body

EXPLODED VIEW

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These

parts are identified by in the Schematic Diagram and EXPLODED VIEW.

It is essenti al that these special safet y parts shoul d be replac ed with the same compo nents as

recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.

Do not modify the original design without permission of manufacturer.

IMPORTANT SAFETY NOTICE

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

MT5398_TS_OUT[1]

CI_ADDR[5]

EMMC_DATA[6]

MT5398_TS_OUT[6]

CI_ADDR[4]

FE_DEMOD1_TS_DATA[1]

MT5398_TS_OUT[4]

CI_ADDR[12]

EMMC_DATA[3]

CI_DATA[1]

FE_DEMOD1_TS_DATA[6]

MT5398_TS_OUT[3]

CI_DATA[5]

EMMC_DATA[4]

FE_DEMOD1_TS_DATA[0]

CI_ADDR[6]

CI_ADDR[11]

MT5398_TS_OUT[2]

CI_ADDR[10]

CI_DATA[2]

MT5398_TS_OUT[7]

CI_ADDR[14]

CI_ADDR[9]

MT5398_TS_OUT[0]

FE_DEMOD1_TS_DATA[3]

EMMC_DATA[5]

CI_ADDR[13]

EMMC_DATA[2]

FE_DEMOD1_TS_DATA[5]

CI_DATA[3]

CI_DATA[6]

CI_DATA[0]

CI_ADDR[7]

CI_DATA[7]

CI_ADDR[8]

CI_ADDR[1]

EMMC_DATA[7]

FE_DEMOD1_TS_DATA[4]

CI_ADDR[2]

FE_DEMOD1_TS_DATA[7]

MT5398_TS_OUT[5]

CI_ADDR[0-14]

FE_DEMOD1_TS_DATA[2]

CI_DATA[4]

CI_ADDR[0]

CI_ADDR[3]

R111 33

EMMC_RST

SMARTCARD_RST/SD_EMMC_DATA[2]

M_RFModule_RESET

AVDD_33SB

SMARTCARD_RST/SD_EMMC_DATA[2]

+3.3V_NORMAL

OPCTRL7

R189

10K

OPT

I2C_SCL4

R125 4.7K

OPT

R134 33

MT5398_XTAL_OUT

MT5398_MIVAL_ERR

STB_SDA

OPCTRL_11_SCL

R107

4.7K

MTK_HD

OPCTRL_10_SDA

/USB_OCD1

MODEL_OPT_5

I2C_SCL5

R183

4.7K

MT5398_XTAL_OUT

R109 33

R128

4.7K

MODULE_V12

R184

4.7K

EMMC_CMD

OSCL0

I2C_SCL6

R185

10K

EMMC_DATA[0]

R177

4.7K

OPT

R142

2.7K

HP_DET

MODEL_OPT_6

EMMC_CLK

/USB_OCD3

R132

2.7K

R135 33

C112

4.7uF

10V

/PCM_OE

R104

4.7K

NON_FRC_60Hz

R112 33

AMP_RESET_SOC

R123

4.7K

Country_AJJA

R117 33

/S2_RESET

SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]

I2C_SDA6

FE_LNA_Ctrl1

AVDD_33SB

+3.3V_NORMAL

/PCM_REG

STB_SCL

OPC_EN

R187

4.7K

OPT

MT5398_TS_IN[5]

I2C_SDA_MICOM

R160

OPT

OPCTRL_1_SCL

+3.3V_NORMAL

R149

4.7K

MTK_EPI

R127 22

OPT

SC_DET

R178

CI_ADDR[0-14]

EMMC_CLK

SMARTCARD_DET/SD_EMMC_DATA[3]

I2C_SDA5

R140

4.7K

MTK_DVB_T2_TUNER

R126 22

OPT

L/DIM0_SCLK

R174

4.7K

OPT

SMARTCARD_DET/SD_EMMC_DATA[3]

I2C_SDA5

IC101

M24C16-R

OPT

NC_3

NC_2

VSS

NC_1

SDA

SCL

VCC

OSCL0

R108

4.7K

MTK_FHD

SOC_RX

R147

2.7K

SMARTCARD_VCC/SD_EMMC_CMD

OSDA1

R193 4.7K

R146

4.7K

DDR_0.78G

OPCTRL3

R173

PWM1_PULL_DOWN_1K

R124

1.2K

R182

OSDA1

AV1_CVBS_DET

R100

4.7K

OPT

R136

4.7K

MTK_NON_CP_BOX

USB_CTL3

MODEL_OPT_0

PWM_DIM1

OSDA0

SOC_RESET

+3.3V_NORMAL

USB_CTL1

LED_PWM0

R137

4.7K

MTK_CP_BOX

C107

4.7uF

10V

SMARTCARD_DATA/SD_EMMC_CLK

I2C_SDA4

+3.3V_NORMAL

EMMC_DATA[1]

MODEL_OPT_6

OPCTRL_0_SDA

MODEL_OPT_0

I2C_SCL2

EPI_LOCK6

R106

4.7K

FRC_120Hz

OSCL2

C100

0.1uF

OPT

16V

R170

10K

/PCM_CE1

MODEL_OPT_5

EMMC_DATA[2-7]

/PCM_WE

R179

PWM_DIM2

C117

0.1uF

16V

R188

4.7K

R119 33

SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]

R113 33

I2C_SDA1

R169

10K

NON_EU

I2C_SCL1

PWM_DIM2

R186

OSDA0

/PCM_IRQA

CI_A_VS1

R168

10K

C109

0.1uF

C111

0.1uF

CTS

IC100

AT24C256C-SSHL-T

NVRAM_ATMEL

GND

SDA

SCL

VCC

MODEL_OPT_7

R143

4.7K

MTK_NON_DVB_S_TUNER

R152

2.7K

NON_TU_Q_KR

+3.3V_NORMAL

MT5398_TS_IN[2]

R151

2.7K

R141

2.7K

R163

MT5398_MCLKI

OPCTRL_10_SDA

MT5398_TS_CLK

MODEL_OPT_3

MODEL_OPT_8

RTS

R150

2.7K

SMARTCARD_VCC/SD_EMMC_CMD

FE_DEMOD1_TS_DATA[0-7]

MODEL_OPT_7

MODEL_OPT_3

R155

R110 33

MT5398_TS_VAL

FE_LNA_Ctrl2

OPCTRL3

AVDD_33SB

STB_SCL

OPCTRL_0_SDA

R139

4.7K

MTK_NON_DVB_T2_TUNER

SC_ID_SOC

/PCM_IOWR

SMARTCARD_CLK/SD_EMMC_DATA[0]

R101

4.7K

SMARTCARD_DATA/SD_EMMC_CLK

R161

OPT

/PCM_WAIT

OSCL1

R115 33

OSCL1

+3.3V_NORMAL

R122

4.7K

Non_Country_AJJA

R114 33

MT5398_XTAL_IN

R138

2.7K

IC100-*2

R1EX24256BSAS0A

NVRAM_RENESAS

VSS

SDA

SCL

VCC

MODEL_OPT_10

COMP1_DET

R130

4.7K

MODULE_V13

OSDA2

MT5398_TS_IN[7]

R156

R176

PWM2_PULL_DOWN_1K

/TU_RESET1

MT5398_TS_IN[1]

LED_PWM1

R116 33

OPCTRL_1_SCL

AMP_RESET_N

IC100-*1

M24256-BRMN6TP

NVRAM_ST

VSS

SDA

SCL

VCC

SOC_TX

L/DIM0_MOSI

RF_SWITCH_CTL

/CI_CD2

STB_SDA

MODEL_OPT_2

MT5398_TS_IN[3]

R105

4.7K

Country_TW

I2C_SDA2

R154

OPT

MODEL_OPT_1

L/DIM0_VS

MT5398_TS_IN[0]

LED_PWM0

/S2_RESET

FE_DEMOD1_TS_CLK

/CI_CD1

+3.3V_NORMAL

R144

4.7K

NON_DDR_0.78G

CI_DATA[0-7]

R102

4.7K

OPT

FE_DEMOD1_TS_VAL

R103

4.7K

NON_Country_TW

MT5398_TS_IN[6]

/PCM_IORD

R129

4.7K

MTK_DDR_1.5GB

AMP_RESET_SOC

/USB_OCD2

I2C_SCL5

R145

4.7K

MTK_DVB_S_TUNER

R153

2.7K

NON_TU_Q_KR

MT5398_MISTRT

R121

1.2K

R158

OPCTRL_11_SCL

MT5398_TS_IN[4]

MODEL_OPT_9

M_REMOTE_RX

SMARTCARD_CLK/SD_EMMC_DATA[0]

C110

0.1uF

I2C_SCL1

+3.3V_NORMAL

I2C_SCL_MICOM

MT5398_TS_SYNC

WOL/ETH_POWER_ON

M_REMOTE_TX

I2C_SDA1

MT5398_TS_OUT[0-7]

R162

R118 33

OPCTRL7

R148

4.7K

MTK_NON_EPI

MT5398_XTAL_IN

FE_DEMOD1_TS_SYNC

R133

2.7K

PCM_RST

R131

4.7K

MTK_DDR_1.25GB

R120 33

R157

OPT

VDD3V3

LED_PWM1

R190

10K

D100

100V

1N4148W

OTP_WRITE

R180

4.7K

+3.3V_NORMAL

OTP_WRITE

VDD3V3

R194

10K

R195

10K

Q100

PMV48XP

C115-*1

2.7pF

50V

ATSC_2.7pF

C114-*1

2.7pF

50V

ATSC_2.7pF

#SIL_RESET

R153-*1

1.5K

TU_Q_KR

R152-*1

1.5K

TU_Q_KR

C114

1.0pF

50V

DVB_1pF

C115

1.0pF

50V

DVB_1pF

X100

27MHz

GND_2

X-TAL_1

GND_1

X-TAL_2

/RST_HUB

CAM_SLIDE_DET

R196

240

IC105

LGE2122[A2_M13]

JTCK

AK10

JTDI

AK11

JTDO

AL9

JTMS

AJ11

JTRST

AJ12

OSDA0

AH11

OSCL0

AH10

OSDA1

AF11

OSCL1

AG11

XTALI

AN29

XTALO

AM29

AVDD33_XTAL_STB

AN30

AVSS33_XTAL_STB

AL29

AVDD33_VGA_STB

AN17

AVSS33_AVSS33_VGA_STB

AL17

AVDD33_PLL

AL26

AVSS33_PLLGP

AC21

AVSS33_CPUPLL

H21

AVDD10_LDO

AM17

AVDD10_ELDO

AN16

U0TX

AH15

U0RX

AH14

U1TX

AH13

U1RX

AG13

POWE

D24

POOE

B25

POCE1

D25

POCE0

A25

PDD7

C22

PDD6

B22

PDD5

A22

PDD4

C23

PDD3

A23

PDD2

B23

PDD1

D23

PDD0

C24

PARB

C25

PACLE

A26

PAALE

B26

EMMC_CLK

C21

OPWRSB

AL15

ORESET

AK20

OIRI

AF17

FSRC_WR

C20

STB_SCL

AL14

STB_SDA

AK15

POR_BND

AE14

IC105

LGE2122[A2_M13]

GPIO0

B30

GPIO1

A31

GPIO2

B31

GPIO3

A32

GPIO4

C30

GPIO5

A33

GPIO6

B32

GPIO7

C31

GPIO8

E30

GPIO9

F29

GPIO10

F27

GPIO11

F28

GPIO12

C32

GPIO13

F30

GPIO14

F32

GPIO15

D30

GPIO16

D32

GPIO17

F31

GPIO18

F33

GPIO19

E31

GPIO20

E32

GPIO21

D31

GPIO22

D33

GPIO23

E29

GPIO24

C33

GPIO25

B33

GPIO26

A30

GPIO27

E28

GPIO28

C29

GPIO29

J28

GPIO30

H29

GPIO31

J26

GPIO32

G30

GPIO33

G27

GPIO34

E27

GPIO35

D29

GPIO36

D28

GPIO37

H28

GPIO38

J27

GPIO39

G29

GPIO40

G31

GPIO41

G28

GPIO42

B28

GPIO43

K28

GPIO44

E25

GPIO45

D21

GPIO46

G23

GPIO47

C28

GPIO48

F24

GPIO49

AB8

GPIO50

AA7

GPIO51

AD6

GPIO52

AC8

GPIO53

AC7

GPIO54

AB6

GPIO55

AC6

ADIN0_SRV

AJ23

ADIN1_SRV

AH23

ADIN2_SRV

AE28

ADIN3_SRV

AD28

ADIN4_SRV

AF22

ADIN5_SRV

AK21

ADIN6_SRV

AG24

ADIN7_SRV

AM18

DEMOD_RST

P30

DEMOD_TSCLK

N32

DEMOD_TSDATA0

R27

DEMOD_TSDATA1

T26

DEMOD_TSDATA2

T27

DEMOD_TSDATA3

P26

DEMOD_TSDATA4

R28

DEMOD_TSDATA5

U27

DEMOD_TSDATA6

U26

DEMOD_TSDATA7

R26

DEMOD_TSSYNC

R29

DEMOD_TSVAL

P27

CI_INT

L25

CI_TSCLK

N33

CI_TSDATA0

K26

CI_TSSYNC

N30

CI_TSVAL

N31

PVR_TSCLK

M31

PVR_TSVAL

M27

PVR_TSSYNC

L27

PVR_TSDATA0

M29

PVR_TSDATA1

M30

SPI_CLK1

L30

SPI_CLK

L33

SPI_DATA

L32

SPI_CLE

K27

OPWM2

AL8

OPWM1

AM8

OPWM0

AM9

SD_D0

D27

SD_D1

C27

SD_D2

D26

SD_D3

C26

SD_CMD

A28

SD_CLK

E24

LED_PWM1

AF15

LED_PWM0

AG15

OPCTRL11

AL16

OPCTRL10

AM16

OPCTRL9

AE17

OPCTRL8

AG19

OPCTRL7

AH17

OPCTRL6

AE19

OPCTRL5

AH19

OPCTRL4

AK16

OPCTRL3

AG17

OPCTRL2

AJ17

OPCTRL1

AF19

OPCTRL0

AJ19

R152-*2

1.2K

TU_N_TW/BR

R153-*2

1.2K

TU_N_TW/BR

MID_MAIN_1

2011.12.13

HDCP EEPROM

CI SLOT -> SOC

MODEL_OPT_4

I2C

NON_DDR_0.78G

GPIO45(EMMC_RST) is dedicated to reset

EMMC for improving A1’s leakage current

X-TAL

DDR_1.25G

MODEL_OPT_4

Support

CI SLOT -> SOC

NVRAM

Write Protection

- Low : Normal Operation

- High : Write Protection

Not Support

CP BOX

CI SLOT -> SOC

SOC -> CI SLOT

EAX64797001* : LD33B

EAX64872101* : LA33B

Support

MODEL_OPT_2

Disable

Non_AJJA

Module

EPI

Close to eMMC Flash

(IC8100)

Enable

MODEL_OPT_8

MODEL_OPT_9

Model Option

EXTERNAL DEMOD

-> SOC

AJJA

T2 Tuner

MODEL_OPT_5

DDR_1.5G

MODEL_OPT_7

Not Support

MODEL_OPT_6

DDR

Wake On Lan

Not Support

STRAPPING LED_PWM0 LED_PWM1 OPCTRL3 OPCTRL7

ICE mode + 27M + serial boot 1 0 0 0

ICE mode + 27M + ROM to Nand boot 1 0 0 1

ICE mode + 27M + ROM to 60bit ECC Nand boot 1 0 1 0

ICE mode + 27M + ROM to eMMC boot from 1 0 1 1

EMMC pins (share pins w/s NAND)

ICE mode + 27M + ROM to eMMC 1 1 0 0

Boot from SDIO pins

Support

SOC -> CI SLOT

FHD

MODEL_OPT_3

DDR

MODEL_OPT_10

CI SLOT -> SOC

S Tuner

5V Tolerance

I2C_1 : AMP, L/DIMMING,HDCP KEY

I2C_2 : T-CON,

I2C_3 : MICOM

I2C_4 : S/Demod,T2/Demod, LNB, MHL(Sil1292)

I2C_5 : NVRAM

I2C_6 : TUNER_MOPLL(T/C,ATV)

MODEL_OPT_1

Non_TWMODEL_OPT_0

No FRC(60Hz)

LOWHIGH

FRC(120Hz)

Country_TW

FRC

V12V13

Panel

Country_AJJA

DDR_0.78G

MODEL_OPT_5

MODEL_OPT_9

DDR_1.25G DDR_1.5G DDR_0.768G

High

Low

High

MODEL_OPT_4

Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

MT5398_TS_OUT[5]

CI_DATA[7]

CI_ADDR[13]

CI_ADDR[14]

MT5398_TS_OUT[1]

CI_ADDR[2]

CI_DATA[4]

CI_ADDR[10]

CI_ADDR[8]

MT5398_TS_OUT[2]

CI_ADDR[6]

CI_ADDR[7]

MT5398_TS_OUT[3]

CI_DATA[6]

CI_ADDR[5]

CI_DATA[3]

MT5398_TS_OUT[4]

CI_ADDR[12]

MT5398_TS_OUT[0]

CI_ADDR[3]

CI_DATA[5]

CI_DATA[1]

CI_DATA[2]

CI_ADDR[9]

MT5398_TS_OUT[6]

CI_ADDR[1]

CI_DATA[0]

CI_ADDR[0]

CI_ADDR[4]

CI_ADDR[11]

MT5398_TS_OUT[7]

TP308

C386

27pF

50V

OPT

TXA2P

COMP1_Y/AV1_CVBS_SOC

TXD1P

USB_DP3

SC_CVBS_IN_SOC

MODEL_OPT_9

TP304

TP335

C360 0.047uF

MODEL_OPT_10

C341

0.047uF

TU_S/N/Q_T/US/KR/TW

SCART_Lout_SOC

C3751500pF

TP354

USB_DM2

MT5398_TS_IN[4]

TP360

TP374

C377

1200pF

HP_OUT

C378

10pF

50V

TXD2P

SCART_Rout_SOC

VDD3V3

+1.2V_MTK_AVDD

TP376

TXCCLKN

TP378

R3701.2K

HP_OUT

TU_CVBS

AVDD3V3_AADC

TXC1P

C302

0.1uF

C365

10uF

10V

TXC3N

COMP1_Pr_SOC

TXDCLKN

C363

1uF

10V

C303

0.1uF

TXC4P

C392

27pF

50V

OPT

TXD1N

WIFI_DP

HP_LOUT_AMP

SCART_Rout_SOC

D2+_HDMI3_JACK

TXD4P

C355

0.047uF

TU_S/N/Q_T/US/KR/TW

TXC2N

TP347

TXD4N

TP333

TXA1P

DDC_SDA_1_SOC

C350

0.1uF

TP367

R3511.2K

HP_OUT

R3490

OPT

R339

2.2K

OPT

/CI_CD1

C391

27pF

50V

OPT

MT5398_MISTRT

TP373

TP312

SC_COM_SOC

TP357

R329

470K

OPT

C399

0.1uF

16V

OPT

EPHY_RDN

+1.2V_MTK_AVDD

R371 100

D0-_HDMI1_SOC

TP310

COMP1_Y/AV1_CVBS_SOC

TP338

MT5398_TS_IN[1]

COMP1_Pb_SOC

D0+_HDMI1_SOC

TXDCLKP

GCLK_SOC

CK+_HDMI1_SOC

C328

0.1uF

PCM_5V_CTL

TP340

HP_LOUT

WIFI_DM

OSDA2

C352 0.01uF

TU_A_GLOBAL_6/7

C304

0.1uF

TP336

SC_L_IN_SOC

D1-_HDMI1_SOC

AUD_MASTER_CLK

TP331

EPHY_TDP

/PCM_REG

C3740.01uF

COMP1_COM_SOC

COMP1_Y/AV1_CVBS

C351

0.1uF

COMP1/AV1/DVI_R_IN

D1-_HDMI3_JACK

TP369

/PCM_OE

TXA3P

R353

C396

33pF

OPT

TP311

TXD0P

AVDD3V3_AADC

/PCM_WE

COMP1/AV1/DVI_R_IN_SOC

TP318

TXD2N

TP363

COMP1_Pr_SOC

/PCM_WAIT

TP330

R340 100

TU_A_GLOBAL_6/7

C342

100pF

50V

USB_DM1

TXB3N

SC_L_IN_SOC

C336

1uF

10V

TU_S/N/Q_T/US/KR/TW

TP349

TP370

R331

TU_S/N/Q_T/US/KR/TW

TP313

TXC0N

TP323

TXD3P

TP383

COMP1/AV1/DVI_L_IN_SOC

VDD3V3

SC_G_SOC

C382

0.1uF

R309

100K

TP326

TP328

TP368

TP303

PMIC_RESET

TXC1N

TXA1N

+5V_NORMAL

TXB3P

TP342

TXB4P

R307 1K

SC_R_SOC

R335 51

TU_S/N/Q_T/US/KR/TW

HP_ROUT_AMP

CI_ADDR[0-14]

TP305

C364

0.1uF

/PCM_IORD

MT5398_TS_OUT[0-7]

TP309

CI_A_VS1

TXD3N

TP322

COMP1/AV1/DVI_L_IN_SOC

SC_FB_SOC

D1+_HDMI1_SOC

TP346

R341 100

SC_R_IN_SOC

R3691.2K

HP_OUT

5V_HDMI_3_JACK

TP316

R381

1/16W

TP379

MODEL_OPT_2

TP320

C332

0.22uF

10V

HP_OUT

C394

27pF

50V

OPT

CK-_HDMI1_SOC

MODEL_OPT_8

MT5398_MCLKI

C310

33pF

TU_S/N/Q_T/US/KR/TW

D2+_HDMI1_SOC

TXC0P

C305

1uF

10V

IF_N

SC_DET

TXB0P

TP343

HDMI_HPD_1_SOC

TXB1P

TP375

R328

470K

OPT

DDC_SCL_3_JACK

COMP1/AV1/DVI_L_IN

R374

DDC_SDA_3_JACK

R366 100

CK-_HDMI3_JACK

TP372

C385

27pF

50V

OPT

MT5398_TS_IN[6]

TXA0N

VDD3V3

TP352

AUD_SCK

AVDD_33SB

TXA2N

TP353

C387

22pF

OPT

USB_DM3

C395

1200pF

HP_OUT

C388

27pF

50V

OPT

USB_DP1

C354

0.1uF

R343

24K

AUD_LRCK

R354

VDD3V3

ARC

R303

AVDD3V3_AADC

C311 1uF

10V

TP365

TP371

TXCCLKP

TP356

PCM_5V_CTL

TXA0P

TXC3P

HP_ROUT

2D/3D_CTL

TP324

TXBCLKP

C3720.01uF

D1+_HDMI3_JACK

C338

560pF

50V

OPT

TP355

AUD_LRCH

R382

+1.2V_MTK_AVDD

TXA3N

VDD3V3

R373

TP300

C312

33pF

TU_S/N/Q_T/US/KR/TW

TXACLKN

R342 10K

TU_S/N/Q_T/US/KR/TW

L304

MT5398_TS_VAL

TP364

TP359

5V_HDMI_1_SOC

TP344

TP319

TP382

C398

0.1uF

16V

OPT

TXACLKP

COMP1_Pb

ARC

R368 100

/PCM_IRQA

R31524K

TP348

COMP1_Pb_SOC

TXB1N

TP345

TP301

SCART_Lout_SOC

TXC2P

R306

R332 10K

TU_S/N/Q_T/US/KR/TW

MT5398_MIVAL_ERR

TP307

TXD0N

CK+_HDMI3_JACK

TP358

VDD3V3

C393

22pF

OPT

CI_DATA[0-7]

TXBCLKN

TP334

TP306

C384

10pF

50V

C306

0.1uF

TXB2N

SPDIF_OUT

SC_B_SOC

R334 51

TU_S/N/Q_T/US/KR/TW

C3730.01uF

R383

TP361

C362

0.1uF

D0-_HDMI3_JACK

TXB2P

SC_R_IN_SOC

TP329

HP_ROUT_MAIN

R367 100

EPHY_TDN

TP321

TP315

R346

TU_S/N/Q_T/US/KR/TW

HDMI_ARC

C390

1200pF

HP_OUT

TP380

USB_CTL2

MT5398_TS_IN[2]

HP_LOUT_MAIN

SC_G_SOC

R344

30K

C358

0.1uF

C383

1200pF

HP_OUT

C389

22pF

OPT

L303

BLM18PG121SN1D

HP_OUT

DTV/MNT_V_OUT_SOC

R302

180

SC_B_SOC

TP366

/PCM_IOWR

TP332

MT5398_TS_IN[5]

IF_P

C307

0.1uF

R308

1.2K

OPT

R345

30K

DDC_SCL_1_SOC

TP337

VCOM_DYN

MT5398_TS_IN[7]

D2-_HDMI3_JACK

C361 1uF

IF_AGC

TP317

TP325

+1.2V_MTK_AVDD

COMP1_COM_SOC

SC_CVBS_IN_SOC

SC_ID_SOC

C331

0.22uF

10V

HP_OUT

MT5398_TS_IN[3]

C337 1uF

10V

TU_S/N/Q_T/US/KR/TW

TP377

C347

0.1uF

TP362

MT5398_TS_CLK

R305

C379

10pF

50V

USB_DP2

L302

BLM18PG121SN1D

HP_OUT

TUNER_SIF

DTV/MNT_V_OUT_SOC

SC_FB_SOC

C359 0.047uF

TU_A_GLOBAL_6/7

SC_COM_SOC

TXA4P

C343

100pF

50V

TXB4N

TXB0N

/PCM_CE1

EPHY_RDP

TP327

R372

R3521.2K

HP_OUT

TP351

SC_R_SOC

C3710.01uF

COMP1_Y/AV1_CVBS_SOC

HDMI_HPD_3_JACK

PCM_RST

TP339

TXA4N

EO_SOC

/CI_CD2

R355

/TU_RESET2

TXC4N

MT5398_TS_IN[0]

TP314

MCLK_SOC

COMP1_Pr

TP341

TP302

D2-_HDMI1_SOC

TP381

MT5398_TS_SYNC

TP350

C339

560pF

50V

OPT

D0+_HDMI3_JACK

OSCL2

GST_SOC

COMP1/AV1/DVI_R_IN_SOC

VDD3V3_HDMI

C345

10uF

16V

C346

10uF

16V

R380

TU_S/N/Q_T/US/KR/TW

DDC_SDA_MHL

5VBUS

HDMI_HPD_4_MHL

DDC_SCL_MHL

D0-_HDMI4_MHL

D0+_HDMI4_MHL

D2-_HDMI4_MHL

D1+_HDMI4_MHL

D2+_HDMI4_MHL

CK-_HDMI4_MHL

D1-_HDMI4_MHL

CK+_HDMI4_MHL

MODEL_OPT_1

R35010

R36151

R36251

R36351

R36451

IC105

LGE2122[A2_M13]

HDMI_CEC

V26

HDMI_0_SCL

AC27

HDMI_1_SCL

AB27

HDMI_2_SCL

AA26

HDMI_3_SCL

W27

HDMI_0_SDA

AC26

HDMI_1_SDA

AB26

HDMI_2_SDA

Y26

HDMI_3_SDA

W26

HDMI_0_PWR5V

AE29

HDMI_1_PWR5V

Y27

HDMI_2_PWR5V

AA28

HDMI_3_PWR5V

V28

HDMI_0_HPD

AD29

HDMI_1_HPD

AA27

HDMI_2_HPD

AA29

HDMI_3_HPD

V29

AVDD12_HDMI_0_RX

AA33

AVDD12_HDMI_1_RX

AA32

AVDD12_HDMI_2_RX

P33

AVDD12_HDMI_3_RX

P32

AVDD33_HDMI

AH33

AVSS33_HDMI_RX_1

AE27

AVSS33_HDMI_RX_2

T25

AVSS33_HDMI_RX_3

W25

AVSS33_HDMI_RX_4

AD27

HDMI_0_RX_0

AG30

HDMI_0_RX_0B

AG31

HDMI_0_RX_1

AF30

HDMI_0_RX_1B

AF31

HDMI_0_RX_2

AE32

HDMI_0_RX_2B

AE33

HDMI_0_RX_C

AG32

HDMI_0_RX_CB

AG33

HDMI_1_RX_0

AD30

HDMI_1_RX_0B

AD31

HDMI_1_RX_1

AC32

HDMI_1_RX_1B

AC33

HDMI_1_RX_2

AC30

HDMI_1_RX_2B

AC31

HDMI_1_RX_C

AE30

HDMI_1_RX_CB

AE31

HDMI_2_RX_0

Y30

HDMI_2_RX_0B

Y31

HDMI_2_RX_1

W32

HDMI_2_RX_1B

W33

HDMI_2_RX_2

W30

HDMI_2_RX_2B

W31

HDMI_2_RX_C

AA30

HDMI_2_RX_CB

AA31

HDMI_3_RX_0

U30

HDMI_3_RX_0B

U31

HDMI_3_RX_1

T32

HDMI_3_RX_1B

T33

HDMI_3_RX_2

T30

HDMI_3_RX_2B

T31

HDMI_3_RX_C

V30

HDMI_3_RX_CB

V31

IC105

LGE2122[A2_M13]

USB_DP_P0

H32

USB_DM_P0

H33

USB_DP_P1

J32

USB_DM_P1

J31

USB_DP_P2

K32

USB_DM_P2

K31

USB_DP_P3

AN10

USB_DM_P3

AM10

AVDD33_USB_P0P1P2

K33

AVDD33_USB_P3

AN8

AVSS33_USB_P1

M25

AVSS33_USB_P3

AE11

TXVP_0

AL13

TXVN_0

AM13

RXVP_1

AL12

RXVN_1

AM12

PHYLED1

AF13

PHYLED0

AJ13

REXT

AN12

AVDD33_ETH

AN14

AVSS33_ELDO

AE13

AVSS33_LD

AC16

AVSS33_COM

AC15

IC105

LGE2122[A2_M13]

TCON0

AA8

TCON1

AA9

TCON2

TCON3

TCON4

TCON5

TCON6

TCON7

AB7

TCON8

TCON9

TCON10

TCON11

TCON12

AVDD12_LVDS_1

AN1

AVDD12_LVDS_2

AN2

AVDD12_LVDS_3

AN3

AVDD33_LVDS

AN4

AVSS12_LVDS_1

AM4

AVSS12_LVDS_2

AM3

AVSS12_LVDS_3

AF5

AVSS33_LVDS_1

AE5

AVSS33_LVDS_2

AC5

AVSS33_LVDS_3

REXT_VPLL

BE0P

BE0N

BE1P

BE1N

BE2P

BE2N

BECKP

BECKN

BE3P

BE3N

BE4P

BE4N

BO0P

AD1

BO0N

AD2

BO1P

AC3

BO1N

AC4

BO2P

AB3

BO2N

AB4

BOCKP

AB1

BOCKN

AB2

BO3P

AA3

BO3N

AA4

BO4P

BO4N

AE0P

AH1

AE0N

AH2

AE1P

AG3

AE1N

AG4

AE2P

AF3

AE2N

AF4

AECKP

AF1

AECKN

AF2

AE3P

AE3

AE3N

AE4

AE4P

AD3

AE4N

AD4

AO0P

AM1

AO0N

AM2

AO1P

AL3

AO1N

AL4

AO2P

AK3

AO2N

AK4

AOCKP

AK1

AOCKN

AK2

AO3P

AJ3

AO3N

AJ4

AO4P

AH3

AO4N

AH4

IC105

LGE2122[A2_M13]

AIN1_R_AADC

AL32

AIN1_L_AADC

AN32

AIN2_R_AADC

AM33

AIN2_L_AADC

AM31

AIN3_R_AADC

AM32

AIN3_L_AADC

AK33

AIN4_R_AADC

AL33

AIN4_L_AADC

AN33

AVDD33_AADC

AJ32

AVSS33_AADC

AC24

VMID_AADC

AN31

MPXP

AH25

AR0_ADAC

AK30

AL0_ADAC

AJ29

AR1_ADAC

AJ31

AL1_ADAC

AK29

AR2_ADAC

AJ30

AL2_ADAC

AH28

AVDD33_ADAC

AJ33

AVSS33_ADAC

AC23

ALIN

AG9

ASPDIF0

AG10

ASPDIF1

V27

AOBCK

AK9

AOLRCK

AJ9

AOMCLK

AF10

AOSDATA4

AH9

AOSDATA3

AK8

AOSDATA2

AJ8

AOSDATA1

AH8

AOSDATA0

AJ10

IC105

LGE2122[A2_M13]

ADCINP_DEMOD

AM27

ADCINN_DEMOD

AN27

AVDD33_DEMOD

AN26

AVDD12_DEMOD

AN28

AVSS33_DEMOD

AL28

AVSS12_DEMOD

AL27

IF_AGC

L26

RF_AGC

M28

LOUTN

AJ27

LOUTP

AK27

OSCL2

N27

OSDA2

N26

CVBS3P

AK26

CVBS2P

AM25

CVBS1P

AH26

CVBS0P

AK25

CVBS_COM

AJ26

AVDD33_CVBS

AM26

AVSS33_CVBS_1

AB20

AVSS33_CVBS_2

AB22

HSYNC

AK18

VSYNC

AL18

AL20

AM20

AL19

COM

AN20

SOG

AK19

VGA_SDA

AG22

VGA_SCL

AH22

COM1

AL21

PB1P

AK22

PR1P

AL22

Y1P

AM21

SOY1

AN21

COM0

AM23

PB0P

AL23

PR0P

AL24

Y0P

AN23

SOY0

AK23

VDACX_OUT

AH24

VDACY_OUT

AJ24

AVDD33_VIDEO

AN25

AVDD12_RGB

AN18

AVSS33_VDAC_BG

AC19

AVSS12_RGB

AK17

AVSS33_VDAC

AE20

ZD306

ADLC 5S 02 015

ZD302

ADLC 5S 02 015

PCB_700*

ZD304

ADLC 5S 02 015

PCB_700*

MID_MAIN_2

2011.12.19

Ready For commercial Audio_L_OUT

1608 sizs For EMI

FOR EMI

Close to JACK

1608 sizs For EMI

1.0Vpp

Close to Main Chip

Place at JACK SIDE

1608 sizs For EMI

For PCB Pattern

1608 sizs For EMI

Close to Tuner

HDMI_CEC

Close to MT5369

PC_R_IN_SOC

For PCB Pattern

PC_L_IN_SOC

Close to Tuner

Near the SOC

Port was changed !!!!

Close to AVDD33_ADAC & AVDD33_AADC

For PCB Pattern

Wake On Lan

Don’t use as GPIO

Ready For commercial Audio_R_OUT

PLACE AT JACK SIDE

Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

L505

BLM18PG121SN1D

AVDD_33SB

LAN_JACK_POWER

Q500

MMBT3904(NXP)

C511

0.1uF

C518

10uF

L503

BLM18PG121SN1D

OPT

VDD3V3

+3.5V_ST_WAKE

C531

0.1uF

16V

C517

10uF

C527

0.1uF

OPT

+1.2V_MTK_CORE

WOL_CTL

C507

0.1uF

+3.3V_NORMAL

POWER_ON/OFF1

C523

0.1uF

C514

10uF

+1.5V_DDR

VDD3V3

TP500

L504

BLM18PG121SN1D

C503

10uF

C535

0.1uF

OPT

+1.5V_DDR

C541

0.1uF

16V

OPT

3.3V_EMMC

+1.2V_MTK_CORE

+3.5V_ST_WAKE

C505

10uF

+1.2V_MTK_CORE

VDD3V3

TP501

R500

10K

+3.5V_ST

C513

10uF

OPT

+1.2V_MTK_AVDD

C508

2.2uF

+3.3V_NORMAL

C504

0.1uF

OPT

C539

0.1uF

OPT

C532

0.1uF

C520

0.1uF

C509

0.1uF

L501

BLM18PG121SN1D

C506

0.1uF

L502

BLM18PG121SN1D

OPT

+1.2V_MTK_CORE

VDD3V3

Q501

PMV48XP

ZD500

OPT

C500

4.7uF

10V

OPT

C501

4.7uF

10V

R502

10K

R501

1.8K

C502

0.1uF

16V

IC500

AP2121N-3.3TRE1

GND

VOUT

VIN

+3.5V_ST_WAKE

C510

0.1uF

16V

AVDD_33SB

C512

1uF

10V

TP502

TP503

IC105

LGE2122[A2_M13]

VCCK_1

L11

VCCK_2

N12

VCCK_3

P12

VCCK_4

AG5

VCCK_5

AH5

VCCK_6

AJ5

VCCK_7

AK5

VCCK_8

AL5

VCCK_9

AM5

VCCK_10

AN5

VCCK_11

AK6

VCCK_12

AL6

VCCK_13

AM6

VCCK_14

AN6

VCCK_15

M11

VCCK_16

N11

VCCK_17

P11

VCCK_18

R11

VCCK_19

M12

VCCK_20

R12

VCCK_21

L13

VCCK_22

L14

VCCK_23

L15

VCCK_24

L17

VCCK_25

L18

VCCK_26

L19

VCCK_27

T11

VCCK_28

U11

VCCK_29

V11

VCCK_30

W11

VCCK_31

Y11

VCCK_32

AA11

VCCK_33

AB11

VCCK_34

AC11

VCCK_35

R23

VCCK_36

L12

VCCK_37

W12

VCCK_38

V23

VCCK_39

Y12

VCCK_40

AF6

VCCK_41

AG6

VCCK_42

AH6

VCCK_43

AJ6

VCCK_44

AE7

VCCK_45

AF7

VCCK_46

AG7

VCCK_47

AD8

VCCK_48

AE8

VCCK_49

AF8

VCCK_50

AE9

VCCK_51

AC10

VCCK_52

AD10

VCCK_53

AD11

VCCK_54

AE10

VCCK_55

AF9

VCCK_56

AG8

VCCK_57

AH7

VCCK_58

AJ7

VCCK_59

AK7

VCCK_60

AL7

VCCK_61

AM7

VCCK_62

AN7

VCCK_63

L16

VCCK_64

V12

VCCK_65

U12

VCCK_66

T12

VCCK_67

AD13

VCCK_68

AD17

VCCK_69

AD14

VCCK_70

AB12

VCCK_71

AA12

VCCK_72

AC12

VCC3IO_C

VCC3IO_B_1

Y10

VCC3IO_B_2

AA10

VCC3IO_A_1

D22

VCC3IO_A_2

E22

DVSS_1

AC18

DVSS_2

AB21

DVSS_3

AB14

DVSS_4

N13

DVSS_5

P13

DVSS_6

R13

DVSS_7

T13

DVSS_8

U13

DVSS_9

V13

DVSS_10

W13

DVSS_11

Y13

DVSS_12

P18

DVSS_13

N14

DVSS_14

P14

DVSS_15

R14

DVSS_16

T14

DVSS_17

U14

DVSS_18

V14

DVSS_19

W14

DVSS_20

Y14

DVSS_21

R18

DVSS_22

N15

DVSS_23

P15

DVSS_24

R15

DVSS_25

T15

DVSS_26

U15

DVSS_27

V15

DVSS_28

W15

DVSS_29

Y15

DVSS_30

AA15

DVSS_31

AB15

DVSS_32

T18

DVSS_33

R16

DVSS_34

T16

DVSS_35

U16

DVSS_36

V16

DVSS_37

W16

DVSS_38

Y16

DVSS_39

AA16

DVSS_40

AB16

DVSS_41

R17

DVSS_42

T17

DVSS_43

U17

DVSS_44

V17

DVSS_45

Y17

DVSS_46

N16

DVSS_47

V18

DVSS_48

Y18

DVSS_49

P16

DVSS_50

V19

DVSS_51

Y19

DVSS_52

W17

DVSS_53

AA17

DVSS_54

AB17

DVSS_55

N19

DVSS_56

AC14

DVSS_57

C13

DVSS_58

K24

DVSS_59

K25

DVSS_60

L24

DVSS_61

M17

DVSS_62

M18

DVSS_63

M19

DVSS_64

P17

DVSS_65

P19

DVSS_66

N18

DVSS_67

U20

DVSS_68

V20

DVSS_69

W20

DVSS_70

Y20

DVSS_71

AA20

DVSS_72

R19

DVSS_73

T19

DVSS_74

M20

DVSS_75

N20

DVSS_76

U21

DVSS_77

V21

DVSS_78

W21

DVSS_79

Y21

DVSS_80

AA21

DVSS_81

P20

DVSS_82

R20

DVSS_83

T20

DVSS_84

U22

DVSS_85

V22

DVSS_86

W22

DVSS_87

Y22

DVSS_88

AA22

DVSS_89

N21

DVSS_90

P21

DVSS_91

R21

DVSS_92

T21

DVSS_93

M22

DVSS_94

N22

DVSS_95

P22

DVSS_96

R22

DVSS_97

T22

DVSS_98

M21

DVSS_99

AC17

DVSS_100

AA19

DVSS_101

M13

DVSS_102

M14

DVSS_103

M15

DVSS_104

AA13

DVSS_105

AB13

DVSS_106

AA14

DVSS_107

AB19

DVSS_108

DVSS_109

W19

DVSS_110

U19

DVSS_111

N17

DVSS_112

DVSS_113

AB18

DVSS_114

AA18

DVSS_115

W18

DVSS_116

U18

DVSS_117

D16

DVSS_118

AC13

DVSS_119

M16

DVSS_120

AC20

DVSS_121

AC22

DVSS_122

AD20

DVSS_123

Y23

DVSS_124

AA23

DVSS_125

AB23

DVSS_126

V24

DVSS_127

W23

2011.12.09

MID_MAIN_3

DECAP FOR SOC (HIDDEN - UCC) DECAP FOR SOC Rework (BOTTOM)

60mA

5600mA

Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

C611

100pF

50V

R605

C614 0.01uF

SC_ID_SOC

C604

10pF

R607

R629

100K

SCART_Lout

R637

1/16W

R626

30K

C610

100pF

50V

C608

10uF

16V

R631

100K

C612 0.01uF

R623 100

C607

100pF

R614

1/16W

R610

51K

1/16W

SC_R_SOC

SC_CVBS_IN

R601

470K

OPT

SC_B_SOC

SC_FB

SC_R_IN

C603

330pF

50V

OPT

C605

10pF

R609

SC_L_IN_SOC

R608

R604

C600

220pF

OPT

TP600

SC_FB_SOC

C615 0.01uF

SCART_Rout

C601

10pF

OPT

C616 0.047uF

R600

C609

10uF

16V

SCART_Rout_SOC

R617 100

C613 0.01uF

SC_CVBS_IN_IF

R622 100

SC_L_IN

SC_CVBS_IN_IF

SCART_Lout_SOC

R602

470K

OPT

SC_CVBS_IN_SOC

SC_B

DTV/MNT_V_OUT

SC_G

SC_COM_SOC

L611

120-ohm

R606

R625

30K

R613

10K

C602

330pF

50V

OPT

TU_CVBS

C606

10pF

R624

1/16W

DTV/MNT_V_OUT_SOC

R620 100

SC_R_IN_SOC

SC_ID

R621 100

SC_G_SOC

SC_R

R616

R615

OPT

R618

15K EU

R619

15K

SCART_AMP_L_FB

SCART_AMP_R_FB

R635

10K

R636

10K

C619

330pF

50V

C618

330pF

50V

+3.3V_NORMAL

C620

1uF

C621

1uF

C617

100pF

R628

68K

R630

68K

2011.12.30

MID_MAIN_SCART

Close to Main Chip

PLACE AT JACK SIDE

Close to SOC

PLACE AT MAIN SOC SIDE

READY FOR FILTER (EMI)

1608 size For EMI

Close to JACK

PLACE AT IC6000

1608 size For EMI

READY FOR FILTER (EMI)

Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

BRA[2]

BRDQ[2]

ARDQ[14]

ARDQ[22]

BRDQ[0]

ARDQ[24]

ARDQ[11]

ARA[12]

BRDQ[10]

ARDQ[5]

ARA[11]

BRDQ[1]

BRDQ[15]

ARDQ[24]

BRDQ[5]

ARDQ[29]

ARDQ[26]

BRDQ[13]

ARDQ[6]

BRA[8]

BRA[3]

BRDQ[10]

ARDQ[10]

BRA[0]

ARDQ[31]

BRDQ[2]

ARDQ[8]

ARA[13]

BRA[6]

ARDQ[2]

ARDQ[12]

BRA[9]

BRA[1]

BRDQ[3]

BRDQ[13]

ARDQ[3]

ARDQ[6]

ARDQ[0]

BRDQ[4]

ARDQ[3]

BRA[4]

BRDQ[12]

ARDQ[1]

ARDQ[28]

BRDQ[8]

BRA[11]

BRA[13]

BRA[6]

ARDQ[16]

ARA[9]

ARA[8]

ARA[2]

BRDQ[9]

BRA[5]

ARDQ[28]

ARA[10]

BRDQ[7]

ARA[13]

ARDQ[26]

ARDQ[9]

ARA[14]

BRA[11]

ARA[6]

ARDQ[27]

BRDQ[1]

ARDQ[4]

BRA[5]

ARA[11]

ARDQ[13]

ARA[3]

ARDQ[31]

BRA[13]

BRDQ[6]

ARDQ[23]

BRDQ[9]

ARDQ[18]

ARA[4]

ARA[6]

ARA[3]

BRA[4]

BRA[7]

ARA[9]

ARA[3]

ARA[7]

ARDQ[9]

ARDQ[7]

ARDQ[1]

ARDQ[15]

ARA[10]

BRDQ[6]

ARDQ[16]

ARA[8]

BRDQ[15]

ARDQ[30]

ARA[0]

BRDQ[12]

ARDQ[18]

BRA[10]

BRDQ[14]

ARA[13]

ARDQ[2]

ARDQ[27]

ARDQ[21]

ARDQ[7]

BRA[15]

ARA[11]

ARA[5]

BRA[7]

ARDQ[22]

ARA[14]

BRA[1]

ARDQ[29]

ARA[9]

ARDQ[17]

ARA[1]

BRA[12]

ARA[4]

ARA[10]

ARDQ[8]

ARA[0]

ARDQ[19]

ARDQ[20]

ARDQ[30]

ARDQ[10]

ARA[8]

BRDQ[8]

ARDQ[20]

BRA[9]

ARA[5]

ARDQ[15]

ARA[14]

ARA[12]

ARA[7]

BRDQ[5]

ARDQ[12]

ARA[4]

BRDQ[7]

ARDQ[5]

ARDQ[23]

ARDQ[13]

BRA[10]

BRA[8]

BRA[2]

ARDQ[19]

ARA[2]

ARA[12]

BRA[3]

ARDQ[25]

BRDQ[14]

ARA[1]

ARDQ[25]

ARDQ[21]

ARDQ[14]

ARDQ[17]

BRA[0]

BRDQ[0]

ARA[2]

ARDQ[0]

BRDQ[4]

BRDQ[3]

BRA[14]

BRDQ[11]

ARA[7]

ARA[0]

ARA[1]

ARDQ[4]

BRDQ[11]

BRA[12]

ARA[6]

/ARDQS3

R731

ARDQM2

B_RVREF6

ARDQ[24-31]

C753

0.1uF

/ARDQS2

R704

R703

BRBA1

C709

0.1uF

/BRCLK0

BRDQ[8-15]

ARCLK1

ARDQS0

+1.5V_DDR

/ARDQS2

C735

0.1uF

C755

0.1uF

TP700

R706

C723

0.1uF

C718

0.1uF

R719

/ARCAS

/ARDQS1

BRDQM1

/ARWE

C746

0.1uF

+1.5V_DDR

BRODT

R716

240

BRCLK0

BRBA0

R727

BRREST

A_RVREF3

C714

0.1uF

C754

0.1uF

ARDQM1

VDD3V3

+1.5V_DDR

C708

10uF

10V

BRDQS0

ARDQ[16-23]

BRCKE

C728

0.1uF

ARDQM3

R705

/BRDQS1

R714

100

ARBA2

ARODT

ARDQ[8-15]

/BRWE

A_RVREF1

+1.5V_DDR

C701

10uF

10V

/ARDQS0

ARDQS0

A_RVREF4

ARDQS1

/BRRAS

/ARCAS

R712

100

BRDQS1

BRDQ[0-7]

ARDQM1

ARDQ[24-31]

C747

0.1uF

+1.5V_DDR

BRA[0-15]

/BRDQS1

/ARCLK0

ARBA1

ARDQ[0-7]

ARDQS3

ARCLK0

/ARWE

C707

10uF

10V

C722

0.1uF

RVREF_A

+1.5V_DDR

/ARCLK1

R711

240

BRODT

R713

100

BRBA0

R720

ARDQ[8-15]

ARDQ[0-7]

R730

C715

0.1uF

A_RVREF2

ARDQS2

C713

0.1uF

C734

0.1uF

+1.5V_DDR

ARBA0

C733

0.1uF

BRDQS1

C711

0.1uF

/ARCS

BRA[0-14]

/BRCS

ARCLK0

ARBA1

RVREF_C

C719

0.1uF

ARA[0-14]

BRCKE

R726

ARDQS3

C742

0.1uF

ARODT

ARDQM3

C725

0.1uF

BRDQM0

+1.5V_DDR

C751

0.1uF

+1.5V_DDR

BRDQ[8-15]

ARBA0

RVREF_A

R707

ARBA2

C720

0.1uF

ARDQS2

BRCLK0

C712

0.1uF

/ARDQS1

/ARCLK0

+1.5V_DDR

/ARCAS

/BRDQS0

/ARRAS

BRBA2

C704

10uF

10V

BRREST

R710

240

ARODT

B_RVREF5

ARDQM2

A_RVREF1

ARBA1

/ARRAS

BRA[15]

+1.5V_DDR

RVREF_C

ARCLK1

R721

/BRWE

R708

R718

B_RVREF5

+1.5V_DDR

/ARCSX

C727

0.1uF

1uF

C703

ARCKE

/ARCSX

ARCKE

/ARCS

/BRCAS

C710

0.1uF

1uF

C706

BRDQS0

C726

0.1uF

/ARWE

C750

0.1uF

C741

0.1uF

/ARDQS0

/BRDQS0

ARCKE

C736

0.1uF

/BRRAS

ARBA0

ARREST

/ARDQS3

1uF

C702

R709

C716

0.1uF

/BRCAS

BRDQM0

1uF

C705

ARDQM0

BRDQM1

ARDQ[16-23]

BRDQ[0-7]

ARA[0-14]

BRBA2

C745

0.1uF

+1.5V_DDR

ARA[0-14]

/ARRAS

+1.5V_DDR

A_RVREF2

A_RVREF3

ARREST

BRBA1

C717

0.1uF

TP701

ARDQS1

A_RVREF4

/BRCLK0

/ARCLK1

ARREST

R702

C700

0.1uF

B_RVREF6

/BRCS

ARDQM0

BRA[14]

ARBA2

K4B2G1646E-BCK0

IC702-*1

DDR_256MB_SS

A10/AP

A11

A12/BC

A13

NC_5

BA0

BA1

BA2

CKE

ODT

RAS

CAS

RESET

DQSL

DQSU

DML

DMU

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

VREFCA

VREFDQ

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDDQ_1

VDDQ_2

VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_9

NC_1

NC_2

NC_3

NC_4

NC_6

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9

K4B4G1646B-HCK0

IC701

DDR_512MB_SS

A10/AP

A11

A12/BC

A13

A15

BA0

BA1

BA2

CKE

ODT

RAS

CAS

RESET

DQSL

DQSU

DML

DMU

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

VREFCA

VREFDQ

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDDQ_1

VDDQ_2

VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_9

NC_1

NC_2

NC_3

NC_4

A14

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9

K4B4G1646B-HCK0

IC703

DDR_512MB_SS

A10/AP

A11

A12/BC

A13

A15

BA0

BA1

BA2

CKE

ODT

RAS

CAS

RESET

DQSL

DQSU

DML

DMU

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

VREFCA

VREFDQ

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDDQ_1

VDDQ_2

VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_9

NC_1

NC_2

NC_3

NC_4

A14

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9

H5TQ4G63AFR-PBC

IC703-*1

DDR_512MB_Hynix

A10/AP

A11

A12/BC

A13

A15

BA0

BA1

BA2

CKE

ODT

RAS

CAS

RESET

DQSL

DQSU

DML

DMU

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

VREFCA

VREFDQ

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDDQ_1

VDDQ_2

VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_9

NC_1

NC_2

NC_3

NC_4

A14

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9

H5TQ4G63AFR-PBC

IC701-*1

DDR_512MB_Hynix

A10/AP

A11

A12/BC

A13

A15

BA0

BA1

BA2

CKE

ODT

RAS

CAS

RESET

DQSL

DQSU

DML

DMU

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

VREFCA

VREFDQ

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDDQ_1

VDDQ_2

VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_9

NC_1

NC_2

NC_3

NC_4

A14

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9

MT41K128M16JT-125:K

IC701-*3

DDR_256MB_MICRON

A10/AP

A11

A12/BC

A13

NC_5

BA0

BA1

BA2

CKE

ODT

RAS

CAS

RESET

DQSL

DQSU

DML

DMU

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

VREFCA

VREFDQ

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDDQ_1

VDDQ_2

VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_9

NC_1

NC_2

NC_3

NC_4

NC_6

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9

MT41K128M16JT-125:K

IC703-*3

DDR_256MB_MICRON

A10/AP

A11

A12/BC

A13

NC_5

BA0

BA1

BA2

CKE

ODT

RAS

CAS

RESET

DQSL

DQSU

DML

DMU

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

VREFCA

VREFDQ

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDDQ_1

VDDQ_2

VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_9

NC_1

NC_2

NC_3

NC_4

NC_6

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9

MT41K256M16HA-125:E

IC701-*2

DDR_512MB_MICRON

A10/AP

A11

A12/BC

A13

NC_5

BA0

BA1

BA2

CKE

ODT

RAS

CAS

RESET

DQSL

DQSU

DML

DMU

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

VREFCA

VREFDQ

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDDQ_1

VDDQ_2

VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_9

NC_1

NC_2

NC_3

NC_4

A14

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9

MT41K256M16HA-125:E

IC703-*2

DDR_512MB_MICRON

A10/AP

A11

A12/BC

A13

NC_5

BA0

BA1

BA2

CKE

ODT

RAS

CAS

RESET

DQSL

DQSU

DML

DMU

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

VREFCA

VREFDQ

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDDQ_1

VDDQ_2

VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_9

NC_1

NC_2

NC_3

NC_4

A14

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9

MT41K128M16JT-125:K

IC702

DDR_256MB_MICRON

A10/AP

A11

A12/BC

A13

NC_5

BA0

BA1

BA2

CKE

ODT

RAS

CAS

RESET

DQSL

DQSU

DML

DMU

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

VREFCA

VREFDQ

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDDQ_1

VDDQ_2

VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_9

NC_1

NC_2

NC_3

NC_4

NC_6

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9

H5TQ2G63DFR-PBC

IC702-*2

DDR_256MB_HYNIX

A10/AP

A11

A12/BC

A13

NC_5

BA0

BA1

BA2

CKE

ODT

RAS

CAS

RESET

DQSL

DQSU

DML

DMU

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

VREFCA

VREFDQ

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDDQ_1

VDDQ_2

VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_9

NC_1

NC_2

NC_3

NC_4

NC_6

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9

IC105

LGE2122[A2_M13]

DDRV_1

DDRV_2

DDRV_3

DDRV_4

DDRV_5

DDRV_6

DDRV_7

DDRV_8

DDRV_9

DDRV_10

D17

DDRV_11

A19

MEMTP

J22

MEMTN

K22

RVREF_A

D18

ARCKE

ARCLK1

ARCLK0

B14

ARCLK0

A14

ARODT

F13

ARRAS

E13

ARCAS

G13

ARCS

G15

ARWE

H18

ARRESET

G16

ARBA0

D15

ARBA1

ARBA2

G18

ARCSX

F15

ARA14

D11

ARA13

F16

ARA12

ARA11

E11

ARA10

ARA9

E16

ARA8

F11

ARA

G17

ARA6

F10

ARA5

E17

ARA4

E10

ARA3

E15

ARA2

F17

ARA1

G10

ARA0

F18

ARDQM0

D12

ARDQS0

D14

ARDQS0

C14

ARDQ0

B17

ARDQ1

D10

ARDQ2

C17

ARDQ3

C10

ARDQ4

C18

ARDQ5

ARDQ6

E18

ARDQ7

ARDQM1

C15

ARDQS1

A13

ARDQS1

B13

ARDQ8

B11

ARDQ9

B16

ARDQ10

A11

ARDQ11

A17

ARDQ12

C12

ARDQ13

A16

ARDQ14

C11

ARDQ15

C16

ARDQM2

ARDQS2

ARDQ16

ARDQ17

ARDQ18

ARDQ19

ARDQ20

ARDQ21

ARDQ22

ARDQ23

ARDQM3

ARDQS3

ARDQ24

ARDQ25

ARDQ26

ARDQ27

ARDQ28

ARDQ29

ARDQ30

ARDQ31

AVDD33_MEMPLL

A20

AVSS33_MEMPLL

IC105

LGE2122[A2_M13]

RVREF_C

BRCLK0

BRCKE

BRODT

BRRAS

BRCAS

BRCS

BRBA0

BRBA1

BRBA2

BRWE

BRA15

BRA14

BRA13

BRA12

BRA11

BRA10

BRA9

BRA8

BRA7

BRA6

BRA5

BRA4

BRA3

BRA2

BRA1

BRA0

DDRV_12

B19

DDRV_13

C19

DDRV_14

D19

DDRV_15

E19

DDRV_16

F19

DDRV_17

G19

DDRV_18

DDRV_19

DDRV_20

DDRV_21

DDRV_22

D13

DDRV_23

DDRV_24

G11

DDRV_25

D20

DDRV_26

E20

DDRV_27

F20

DDRV_28

G20

DDRV_29

DDRV_30

DDRV_31

DDRV_32

DDRV_33

DDRV_34

BRDQM0

BRDQS0

BRDQ0

BRDQ1

BRDQ2

BRDQ3

BRDQ4

BRDQ5

BRDQ6

BRDQ7

BRDQM1

BRDQS1

BRDQ8

BRDQ9

BRDQ10

BRDQ11

BRDQ12

BRDQ13

BRDQ14

BRDQ15

BRRESET

DDR ONE SIDE 12

2011.12.09

Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

CI_MDI[3]

CI_A_DATA[1]

CI_A_DATA[6]

CI_MDI[0]

MT5398_TS_OUT[5]

CI_MDI[1]

CI_A_ADDR[1]

CI_A_DATA[5]

CI_MDI[4]

CI_TS_DATA[7]

CI_TS_DATA[0]

MT5398_TS_IN[7]

CI_ADDR[14]

CI_DATA[7]

MT5398_TS_OUT[4]

CI_A_DATA[7]

CI_ADDR[7]

CI_TS_DATA[6]

CI_A_ADDR[13]

CI_A_ADDR[8]

CI_A_ADDR[11]

MT5398_TS_IN[3]

CI_DATA[2]

CI_A_ADDR[10]

CI_ADDR[6]

CI_DATA[4]

CI_A_ADDR[12]

CI_MDI[4]

CI_MDI[7]

CI_DATA[1]

CI_A_DATA[3]

CI_A_DATA[5]

CI_A_ADDR[4]

CI_TS_DATA[3]

CI_DATA[5]

CI_ADDR[4]

CI_A_DATA[2]

CI_A_DATA[6]

CI_ADDR[12]

CI_A_DATA[0]

CI_ADDR[13]

CI_MDI[7]

MT5398_TS_IN[6]

CI_MDI[6]

CI_MDI[2]

CI_A_ADDR[9]

CI_TS_DATA[4]

CI_A_DATA[3]

CI_A_DATA[7]

MT5398_TS_OUT[0]

CI_ADDR[9]

MT5398_TS_IN[2]

CI_ADDR[0]

CI_MDI[3]

CI_A_ADDR[3]

CI_A_ADDR[7]

CI_A_ADDR[14]

CI_DATA[3]

CI_A_DATA[4]

CI_MDI[6]

CI_MDI[1]

CI_TS_DATA[5]

CI_ADDR[10]

CI_MDI[2]

CI_A_DATA[4]

MT5398_TS_IN[0]

CI_A_ADDR[2]

CI_A_DATA[0]

CI_DATA[6]

CI_A_ADDR[5]

CI_DATA[0]

CI_A_ADDR[0]

CI_MDI[5]

CI_ADDR[8]

CI_A_ADDR[6]

CI_A_DATA[2]

MT5398_TS_OUT[7]

CI_ADDR[3]

MT5398_TS_IN[5]

CI_TS_DATA[2]

CI_MDI[5]

CI_ADDR[11]

MT5398_TS_OUT[6]

CI_ADDR[2]

MT5398_TS_IN[4]

MT5398_TS_IN[1]

MT5398_TS_OUT[2]

MT5398_TS_OUT[3]

MT5398_TS_OUT[1]

CI_A_DATA[1]

CI_TS_DATA[1]

CI_ADDR[1]

CI_ADDR[5]

/PCM_IORD

R924

10K

OPT

AR908 0

/CI_CD2

PCM_RST

/PCM_IRQA

CI_IN_TS_VAL

AR905 0

R939 22

CI_IN_TS_VAL

/PCM_CE1

CI_A_ADDR[10]

R934

10K

OPT

CI_TS_CLK

/PCM_REG

R935

10K

R937

10K

OPT

+5V_CI_ON

CI_TS_DATA[0-7]

/PCM_REG

PCM_INPACK

CI_A_DATA[0-7]

+5V_CI_ON

CI_A_ADDR[12]

R933

10K

OPT

CI_A_ADDR[8]

CI_IN_TS_CLK

CI_A_ADDR[14]

R915

+3.3V_NORMAL

R914

10K

R910

10K

CI_TS_CLK

C904

0.1uF

CI_A_ADDR[5]

R916

R926

OPT

R93122

OPT

/PCM_CE1

R907

R940 22

CI_VS1

C902

12pF

50V

OPT

R922

/PCM_CE2

R936

10K

CI_DATA[0-7]

CI_VS1

CI_A_VS1

CI_VS1

CI_A_ADDR[13]

CI_IN_TS_SYNC

R918

47K

R927

100

CI_A_ADDR[3]

/PCM_OE

R900

10K

OPT

C900

12pF

50V

OPT

C907

0.1uF

16V

MT5398_TS_OUT[0-7]

CI_TS_DATA[2]

R911 22

/PCM_WAIT

R913

47K

+5V_CI_ON

CI_A_ADDR[9]

R929

10K

R917

CI_TS_SYNC

PCM_INPACK

R925

/PCM_WE

R909

MT5398_MISTRT

CI_IN_TS_CLK

/PCM_WE

CI_TS_DATA[5]

MT5398_TS_CLK

PCM_RST

/PCM_CE2

/CI_CD1

/PCM_IOWR

CI_ADDR[0-14]

AR900 47

/PCM_IOWR

CI_TS_DATA[0]

/CI_CD1

R938

OPT

/PCM_IRQA

CI_A_ADDR[2]

AR909 0

AR902

R921

CI_MDI[0-7]

R908

CI_TS_DATA[6]

AR907 0

/PCM_IORD

MT5398_TS_IN[0-7]

CI_IN_TS_SYNC

MT5398_MCLKI

CI_TS_VAL

CI_A_ADDR[1]

/PCM_A_REG

R930

47K

AR901 47

CI_MDI[0-7]

C905

10uF

10V

CI_TS_SYNC

CI_A_ADDR[11]

CI_A_DATA[0-7]

CI_A_ADDR[7]

R906

10K

OPT

R923

10K

OPT

R941 22

CI_A_ADDR[0]

/CI_CD2

R920

OPT

CI_TS_VAL

AR904 0

AR903

CI_TS_DATA[7]

AR906 0

R932 22

OPT

CI_A_ADDR[6]

MT5398_TS_SYNC

/PCM_OE

CI_TS_DATA[3]

R928 100

+3.3V_NORMAL

MT5398_TS_VAL

/PCM_A_REG

/PCM_WAIT

CI_TS_DATA[1]

R919

47K

CI_A_ADDR[4]

C906 0.1uF

CI_TS_DATA[4]

CI_A_ADDR[0-14]

R912 22

MT5398_MIVAL_ERR

R942 22

JK900

10120698-015LF

G1G2

2660

2761

2862

2963

3064

2011.11.21

MID_MAIN_CI

Close to CI Slot

Close to MT5369

Close to MT5398

CI TS INPUT

CI DETECT

Close to CI Slot

CI TS OUTPUT

Close to CI Slot

Only for training and service purposes

LGE Internal Use Only

THERMAL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+5V_NORMAL

L2409

BLM18PG121SN1D

C2430

10uF

16V

C2413

0.1uF

50V

+12V

C2450

0.01uF

50V

POWER_ON/OFF2_3

C2406

0.1uF

16V

+24V

C2418

10uF

10V

R2403

10K

IC2401

NCP803SN293

P_DET_BOTH_12_3.5V

GND

VCC

RESET

+1.5V_DDR

+3.5V_ST

POWER_ON/OFF2_3

C2424

150pF

50V

R2452

1/8W

OPT

C2404

0.1uF

16V

C2453

0.1uF

16V

C2420

0.1uF

16V

R2408

10K

POWER_ON/OFF2_1

POWER_ON/OFF2_2

R2419

100

R2455

47K 1%

Q2407

AO3407A

PANEL_VCC

C2454

10uF

10V

+3.5V_ST

+3.3V_NORMAL

C2411

0.1uF

16V

L2402

CIS21J121

C2435

4.7uF

50V

PWM_DIM1

R2432

330K1/16W 5%

+24V

R2410

2.7K

P_DET_ONLY_12V

PWM_DIM2

C2447

10uF

10V

C2455

0.1uF

16V

POWER_ON/OFF1

R2438

51K

R2411

1.5K

P_DET_BOTH_24_3.5V

R2453

10K

C2410

0.1uF

50V

P_DET_BOTH_12_3.5V

C2451

10uF

10V

C2429

0.1uF

16V

L2407

4.7uH

C2408

10uF

10V

C2433

0.1uF

50V

C2443

0.1uF

50V

C2407

10uF

10V

L2406

BLM18PG121SN1D

RL_ON

C2401

0.1uF

50V

C2403

0.1uF

16V

OPT

Q2401

MMBT3906(NXP)

C2412

0.1uF

16V

L2408

BLM18SG121TN1D

R2416

100K

P_DET_BOTH_12_3.5V

R2431

15K

1/16W 5%

+3.5V_ST

C2440

1uF

25V

OPT

+24V

C2442

10uF

10V

R2418

100

P_DET_BOTH_12_3.5V

R2451

1/8W

OPT

C2438

10uF

10V

PANEL_CTL

+3.5V_ST

PANEL_VCC

R2406

10K

C2448

10uF

10V

R2409

1.2K

P_DET_ONLY_12V

R2417

100K

L2400

BLM18PG121SN1D

R2421

10K

OPT

+12V

L2405

BLM18PG121SN1D

C2431

10uF

16V

C2439

10uF

10V

Q2406

MMBT3904(NXP)

C2422

0.1uF

50V

C2441

47pF

50V

OPT

R2402

6.8K

POWER_ON/OFF2_2

C2436

0.1uF

16V

+12V

C2402

10uF

16V

+3.5V_ST

C2419

0.1uF

16V

+1.2V_MTK_CORE

R2401

10K

L2404

2uH

C2400

10uF

16V

R2436

16K

R2433

56K

1/16W

C2432

0.01uF

50V

C2434

0.1uF

16V

OPT

C2428

10uF

10V

C2414

10uF

10V

R2430

10K

R2437

10K

R2427

30K

C2444

10uF

10V

C2456

10uF

10V

R2428

10K

POWER_DET

R2412

8.2K

P_DET_BOTH_24_3.5V

L2401

CIS21J121

C2409

10uF

10V

R2439

10K

R2454

1/16W

OPT

VDD3V3_HDMI

C2427

0.1uF

16V

+3.3V_NORMAL

POWER_ON/OFF2_4

D2401

40V

B540C

C2423

0.01uF

50V

+12V

L2403

CIS21J121

C2421

4700pF

50V

IC2402

NCP803SN293

GND

VCC

RESET

R2414

10K

POWER_ON/OFF1

+12V

C2457

0.1uF

16V

R2413

P_DET_BOTH_24_3.5V

C2452

100pF

50V

POWER_ON/OFF2_1

R2404

5.1K

R2400

P_DET_BOTH_12_3.5V

+3.5V_ST

P2401

SMAW200-H18S1

POWER_18P

12V

24V

PDIM#1

GND

12V

GND

3.5V

GND

INV ON

24V

GND

PDIM#2

PWR ON

12V

24V

3.5V

+3.3V_NORMAL

R2425

100

INV_CTL

R2426

L2411

2.2uH

NR5040T2R2N

IC2403

TPS54319TRE

VIN_1

GND_1

COMP

SS/TR

PH_1

PH_2

PH_3

BOOT

PWRGD

VIN_3

AGND

RT/CLK

VSENSE

GND_2

VIN_2

EP[GND]

C2417

10uF

35V

IC2404

RT8289GSP

NC_2

NC_1

BOOT

GND

VIN

[EP]GND

IC2400

BD86106EFJ

AGND

VIN

PGND

COMP

SW_1

SW_2

[EP]

C2405

0.0068uF

50V

ZD2400

OPT

JP2408

JP2409

JP2410

JP2411

L2410

2uH

NR8040T2R0N

IC2405

TPS54327DDAR

VREG5

VFB

GND

VBST

VIN

[EP]GND

C2445

100pF

50V

OPT

C2415

1uF

10V

C2416

3300pF

50V

C2437

0.1uF

16V

C2425

22uF

10V

125C

C2426

22uF

10V

125C

P2400

SMAW200-H24S2

POWER_24P

GND

L/DIMO_VS

L/DIM0_MOSI

L/DIM0_SCLK

L/DIM0_VS_PWR

L/DIM0_SCLK_PWR

L/DIM0_MOSI_PWR

L/DIM0_VS

L/DIM0_SCLK

L/DIM0_MOSI

R2456

L/DIM_OUT

R2457

4.7K

L/DIM_OUT

R2458

L/DIM_OUT

R2459

L/DIM_OUT

L/DIM0_MOSI_PWR

L/DIM0_VS_PWR

L/DIM0_SCLK_PWR

ZD2401

OPT

ZD2402

OPT

R2410-*1

2.7K

P_DET_BOTH_12_3.5V

R2409-*1

1.2K

P_DET_BOTH_12_3.5V

IC2401-*1

NCP803SN293

P_DET_BOTH_24_3.5V

GND

VCC

RESET

R2416-*1

100K

P_DET_BOTH_24_3.5V

R2418-*1

100

P_DET_BOTH_24_3.5V

R2410-*2

2.7K

P_DET_BOTH_12_24V

R2409-*2

1.2K

P_DET_BOTH_12_24V

R2412-*1

8.2K

P_DET_BOTH_12_24V

R2411-*1

1.5K

P_DET_BOTH_12_24V

R2416-*2

100K

P_DET_BOTH_12_24V

IC2401-*2

NCP803SN293

P_DET_BOTH_12_24V

GND

VCC

RESET

R2418-*2

100

P_DET_BOTH_12_24V

C2410-*1

0.1uF

50V

P_DET_BOTH_24_3.5V

C2410-*2

0.1uF

50V

P_DET_BOTH_12_24V

R2442

33K

R2441

5.6K

R2440

3.3K

1/16W

Q2408

NTR4501NT1G

MID_POWER

2011.11.25

HDMI LEAKAGE Workaround in MTK A2(A0) (Default= with HDMI_LEAKAGE)

DDR MAIN 1.5V

12V-->3.58V

Vout=1.222*(1+R1/R2)

Vout=0.8*(1+R1/R2)

+5V_Normal

ST_3.5V-->3.5V

DDR MAIN 1.5V

Vout=0.827*(1+R1/R2)=1.521V

PANEL_POWER

TYP 1450mA

FROM LPB & PSU

Placed on SMD-TOP

24V-->3.48V

MAX 3.4 A

not to RESET at 8kV ESD

Power_DET

+3.3V_NORMAL

Vout=0.765*(1+R1/R2)

Placed on SMD-TOP

On-semi

Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

WOL/WIFI_POWER_ON

POWER_ON/OFF1

R3005 10K

MICOM_LCD/OLED

R3004 10K

MICOM_GP3_12/15PIN

I2C_SDA_MICOM

MODEL1_OPT_5

RUE003N02

Q3001

HDMI_CEC_FET_ROHM

+3.5V_ST

R3030

10K

R3014 10K

MICOM_DEBUG

+3.5V_ST

WOL_CTL

C3003 8pF

P3000

12507WS-04L

MICOM_DEBUG

SCART_MUTE

CAM_CTL

KEY1

MODEL1_OPT_5

CEC_REMOTE

R3012 10K

MICOM_NON_LOGO_LIGHT

POWER_ON/OFF2_4

C3001 0.47uF

SOC_TX

MODEL1_OPT_3

R3013 10K

MICOM_LOGO_LIGHT

R3008 10K

MICOM_TACT_KEY

EDID_WP

CAM_PWR_ON_CMD

LOGO_LIGHT

MODEL1_OPT_1

RL_ON

MODEL1_OPT_2

R3007-*2

22K

MICOM_OLED_FRC

SOC_RX

POWER_DET

R3007-*1

56K

MICOM_OLED_MAIN

R3001 10K

MICOM_M13

MHL_DET

MICOM_RESET

CAM_CTL

MODEL1_OPT_4

R3031

270K

OPT

R3010 10K

MICOM_TOUCH_KEY

R3021

10K

EDID_WP

LED_R

MODEL1_OPT_2

C3004

0.1uF

16V

R3028

4.7M

OPT

POWER_ON/OFF2_4

LED_R

R3007 10K

MICOM_PDP

POWER_ON/OFF2_1

LOGO_LIGHT

MICOM_DEBUG

I2C_SCL_MICOM

R3032

10K

R3033

27K

HDMI_CEC

MODEL1_OPT_1

X3000

32.768KHz

C3002

8pF

+3.5V_ST

PANEL_CTL

MODEL1_OPT_3

MHL_DET

C3000

0.1uF

POWER_ON/OFF2_2

AMP_MUTE

R3034

120K

KEY2

CAM_PWR_ON_CMD

SCART_MUTE

D3000

BAT54_SUZHO

POWER_ON/OFF2_3

SI1012CR-T1-GE3

Q3001-*1

HDMI_CEC_FET_VISHAY

SW3000

JTP-1127WEM

MICOM_RESET_SW

4 3

R3002 10K

MICOM_GED

MODEL1_OPT_0

MICOM_DEBUG

MODEL1_OPT_4

R3029 22

MICOM_RESET_22OHM

INV_CTL

+3.5V_ST

SOC_RESET

MODEL1_OPT_0

MICOM_RESET

R3016 1K

+3.5V_ST

GND

SIDE_HP_MUTE

R3003 10K

MICOM_H13

HDMI_CEC

R3000 10K

MICOM_NON_GED

R3006 10K

MICOM_NC4_8PIN

R3029-*1 33

MICOM_RESET_33OHM

ST_BY_DET_CAM

+3.5V_ST

WOL/ETH_POWER_ON

IC3000

R5F100GEAFB

MICOM_LEAD_Au

P60/SCLA0

P61/SDAA0

P62

P63

P31/TI03/TO03/INTP4

P75/KR5/INTP9/SCK01/SCL01

P74/KR4/INTP8/SI01/SDA01

P73/KR3/SO01

P72/KR2/SO21

P71/KR1/SI21/SDA21

P70/KR0/SCK21/SCL21

P30/INTP3/RTC1HZ/SCK11/SCL11

P50/INTP1/SI11/SDA11

P51/INTP2/SO11

P17/TI02/TO02

P16/TI01/TO01/INTP5

P15/PCLBUZ1/SCK20/SCL20

P14/RXD2/SI20/SDA20

P13/TXD2/SO20

P12/SO00/TXD0/TOOLTXD

P11/SI00/RXD0/TOOLRXD/SDA00

P10/SCK00/SCL00

P146

P147/ANI18

P27/ANI7

P26/ANI6

P25/ANI5

P24/ANI4

P23/ANI3

P22/ANI2

P21/ANI1/AVREFM

P20/ANI0/AVREFP

P130

P01/TO00/RXD1

P00/TI00/TXD1

P140/PCLBUZ0/INTP6

P120/ANI19

P41/TI07/TO07

P40/TOOL0

RESET

P124/XT2/EXCLKS

P123/XT1

P137/INTP0

P122/X2/EXCLK

P121/X1

REGC

VSS

VDD

IC3000-*1

R5F100GEAFB#30

MICOM_LEAD_Cu

P60/SCLA0

P61/SDAA0

P62

P63

P31/TI03/TO03/INTP4

P75/KR5/INTP9/SCK01/SCL01

P74/KR4/INTP8/SI01/SDA01

P73/KR3/SO01

P72/KR2/SO21

P71/KR1/SI21/SDA21

P70/KR0/SCK21/SCL21

P30/INTP3/RTC1HZ/SCK11/SCL11

P50/INTP1/SI11/SDA11

P51/INTP2/SO11

P17/TI02/TO02

P16/TI01/TO01/INTP5

P15/PCLBUZ1/SCK20/SCL20

P14/RXD2/SI20/SDA20

P13/TXD2/SO20

P12/SO00/TXD0/TOOLTXD

P11/SI00/RXD0/TOOLRXD/SDA00

P10/SCK00/SCL00

P146

P147/ANI18

P27/ANI7

P26/ANI6

P25/ANI5

P24/ANI4

P23/ANI3

P22/ANI2

P21/ANI1/AVREFM

P20/ANI0/AVREFP

P130

P01/TO00/RXD1

P00/TI00/TXD1

P140/PCLBUZ0/INTP6

P120/ANI19

P41/TI07/TO07

P40/TOOL0

RESET

P124/XT2/EXCLKS

P123/XT1

P137/INTP0

P122/X2/EXCLK

P121/X1

REGC

VSS

VDD

EYE_SCL

EYE_SDA

R3035

3.3K

EYE_Q_10P

R3036

3.3K

EYE_Q_10P

+3.5V_ST

MICOM

2012.02.22

For CEC

HDMI_WAUP:HDMI_INIT

NON_GED

For Debug

Commercial

POWER_ON/OFF2_4

LCD

MICOM MODEL OPTION

/ OLED

Ready for sample set

PDP

H13

TACT_KEY

IR_wafer(12/15)

GP4 High/MID Power SEQUENCE

Ready for sample set

POWER_ON/OFF2_3

MODEL_OPT_3

M13MODEL_OPT_4

Renesas MICOM

POWER_ON/OFF!

MODEL_OPT_2

MODEL_OPT_0

For LOGO LIGHT

Need to Assign ADC port

MODEL_OPT_5

LOGO

SOC_RESET

POWER_ON/OFF2_2

GED

IR_wafer(10pin)

MODEL_OPT_1

Don’t remove R3014,

not making float P40

MICOM MODEL OPTION

Ready For

NON LOGO

POWER_ON/OFF2_1



TOUCH_KEY

Only for training and service purposes

LGE Internal Use Only

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