Intel® PXA255 Processor
Developer ’s Manual
March, 2003
Order Num ber : 278693-00 1
ii Intel® PXA255 Processor Developer ’s Manual
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Intel® PX A255 Processor De veloper’s Man ual iii
Contents
Conten ts
1 Introduction................. .......... ............. ....................... ........................ .......... ............. .................... . 1-1
1.1 Intel® XScale™ Microa rc hit ec tur e Featur es...... ... ....................... ........................ ..............1-1
1.2 System Integrati on Feat ur es.......... ....................... ....................... ........................ ... ...........1-1
1.2.1 Memory Control ler ............ ....................... ....................... .... ....................... ...........1-2
1.2.2 Clocks and Power Contro llers........ ....................... ........................ ....................... . 1-2
1.2.3 Universal Ser ial Bus (USB) Client......... ....................... ....................... ..................1-2
1.2.4 DMA Controlle r (DMAC) ................ .......... ............. ........................ ....................... .1-3
1.2.5 LCD Contr oller ..................... ....................... .......... .............. ....................... ...........1-3
1.2.6 AC97 Controll e r ............ ........................ ....................... .......... ............. ..................1-3
1.2.7 Inter-IC So und (I2S) Co ntroller ................ .......... ............. ........................ ..............1-3
1.2.8 Multimedia Car d (MMC) Cont roller .................... ............. ........................ ..............1-3
1.2.9 Fast Infrar ed (FIR) Communic a tion Port ...................... ....................... .......... ........1-3
1.2.10 Synchronous Se r ial Protocol Controlle r (SSPC)............. .............. ....................... . 1-4
1.2.11 Inter-Integ rated Circu it (I2C) Bus Interface Unit........ ............. ....................... ........1 -4
1.2.12 GPIO ............. ....................... ....................... ........................ ....................... .......... .1-4
1.2.13 UARTs ................ .......... .............. ....................... ....................... ........................ ....1-4
1.2.14 Real-Time C lock (RTC)..... ....................... ....................... ........................ .......... ....1-5
1.2.15 OS Timers............... ....................... ....................... ........................ .......... ............. . 1-5
1.2.16 Pulse-Width Mo d ulator (PWM) ...... ....................... ........................ ....................... .1-5
1.2.17 Interrupt Co ntrol ...................... ........................ .......... ............. ....................... ........1 -5
1.2.18 Network Synch ronous Seria l Protocol P ort.................. ............. ........................ .... 1-5
2 System Architecture ................... ........................ ....................... ... ........................ .................... ....2-1
2.1 Overview....................... ....................... ........................ ....................... ....................... ........2 -1
2.2 Intel® XScale™ Microa rc hit ec tur e Implemen tat i on Opti o ns............... ... .... ....................... . 2-2
2.2.1 Coprocessor 7 Register 4 - PSFS Bit ................ ....................... .......... .............. .... 2-2
2.2.2 Coprocessor 1 4 Registers 0-3 - Perf ormance Monitori ng......... .............. ..............2-3
2.2.3 Coprocess or 14 Regis ter 6 and 7- Clock and Po wer Management.................. ....2-3
2.2.4 Coprocessor 15 Registe r 0 - ID Reg ister Defi nition ............ ....................... ...........2-3
2.2.5 Coprocessor 15 Registe r 1 - P-Bit .............. .............. ....................... .....................2-4
2.3 I/O Ordering ........... .............. ....................... ....................... .......... .............. .................... .... 2-5
2.4 Semaphores .................... .............. ....................... .......... ............. ........................ ..............2-5
2.5 Interrupts.......... .......... ............. ....................... ........................ ....................... .......... .......... . 2-5
2.6 Reset ..... ............. ....................... .......... .............. ....................... ....................... ..................2-6
2.7 Internal Registe rs....... ... ....................... ........................ ... ....................... ............................2 -7
2.8 Selecting Per ipherals vs. General Purp ose I/O ........... ............. ....................... ..................2-7
2.9 Power on Reset and Boot Operatio n ............. ........................ ... ....................... ..................2-8
2.10 Power Managemen t................... ........................ ....................... .......... ............. ..................2-8
2.11 Pin List ................ ....................... ........................ .......... ............. ....................... ..................2-8
2.12 Memory Map........................ ....................... .......... ............. ........................ .......... ............2-18
2.13 System Archi tecture Regist er Summary ...................... ....................... .......... ............. ...... 2-21
3 Clocks and Powe r Manager ................. .......... .............. ....................... ....................... ..................3-1
3.1 Clock Manager Introduction.............. .......... ............. ........................ ....................... ...........3 -1
3.2 Power Manager I ntroduction.......... ....................... ....................... .......... .............. ..............3-2
3.3 Clock Manager.... ............. ........................ ....................... .......... ............. ........................ .... 3-2
iv Intel® PXA255 Processor Developer’s Manual
Contents
3.3.1 32.768 kHz Oscillator. ... ....................... .... ....................... ....................... ............... 3-4
3.3.2 3.6864 MHz Oscilla tor ..... ........................ ....................... .......... ............. ...............3-4
3.3.3 Core Phase Locked Loop ................. ............. ........................ ....................... ........3-4
3.3.4 95.85 MHz Peri pheral Phase Locked Loop ................. ............. ....................... ..... 3-5
3.3.5 147.46 MHz Per ipheral Phase Locked Loop .................. ............. ........................ . 3-5
3.3.6 Clock Gatin g .............. ............. ....................... ........................ ....................... ........3-6
3.4 Resets and Po wer Modes....... ....................... ....................... ........................ .....................3-6
3.4.1 Hardware Res et...................... ....................... ........................ .......... ............. ........ 3-6
3.4.2 Watchdog R eset .............. ........................ ....................... .......... ............. ...............3-7
3.4.3 GPIO Reset .................. ....................... ........................ ... ....................... ...............3-8
3.4.4 Run Mode ........... ... .... ....................... ....................... ........................ ... ..................3-9
3.4.5 Turbo Mode ............... ............. ....................... ........................ .......... ............. ........ 3-9
3.4.6 Idle Mode ............ ... ........................ ... ....................... ........................ ... ................3-10
3.4.7 Frequency C hange Sequence.................... ............. ........................ ...................3-11
3.4.8 33-MHz Idle Mode .................. ....................... .... ....................... ....................... ... 3-13
3.4.9 Sleep Mode...... ....................... ....................... .......... .............. ....................... ......3-15
3.4.10 Power Mode S ummary .............. .............. ....................... ....................... ............. 3-20
3.5 Power Manager Registers ................... ....................... ........................ ....................... ...... 3-22
3.5.1 Power Manag er Control Re gister (PMCR) .............. .............. ....................... ...... 3-23
3.5.2 Power Manag er General C onfiguration R egister (PCF R)............ .......... .............3-24
3.5.3 Power Manag er Wake-Up Enabl e Register (PWER)............. ....................... ...... 3-25
3.5.4 Power Man ager Rising-E dge Detect En able Regi ster (PRER) ................. .........3-26
3.5.5 Power Manager Fa lling-Edge Detect Ena ble Register (PFER ) ................. .........3-27
3.5.6 Power Manag er GPIO Edge D etect Status Register (PE DR) ....................... ...... 3-28
3.5.7 Power Manag er Sleep Status Register (PSSR) ....................... ....................... ... 3-29
3.5.8 Power Manag er Scratch Pad Register (P SPR) ........... .......... ............. ................3 -30
3.5.9 Power Manager Fast Slee p Walk-u p Co nfig u rati o n Regis ter (PMFW) ...............3-31
3.5.10 P o wer Manage r GP I O Sleep State Registers (PG SR0, PGSR1, PG SR2).. .. . .. . .3 -31
3.5.11 Reset Con troller Statu s Register (RCSR).......... ....................... ....................... ... 3-33
3.6 Clocks Manager Regis te rs...... ... ... ........................ ....................... ....................... .............3 -34
3.6.1 Core Cloc k Configurati on Register ( C CCR) ............ .............. ....................... ...... 3-34
3.6.2 Clock Enable Regis ter (CKEN) ................ ... ....................... ........................ ......... 3-36
3.6.3 Oscillator Configura tio n Registe r (OSCC) ................... ... ....................... .... ......... 3-38
3.7 Coprocessor 14: Clock a nd Power Mana gement ................. .............. ....................... ...... 3-38
3.7.1 Core Cloc k Configurati on Register (CCLKCFG)...... .............. ....................... ...... 3-39
3.7.2 Power Mode R egister (PWRMOD E).............. .......... .............. ....................... ...... 3-40
3.8 External Hardwa r e Consi d erations................... .... ... ....................... ........................ ......... 3-40
3.8.1 Power-On- Reset Consid erations ............. ....................... ....................... .............3 -40
3.8.2 Power Supply Connectivity .................. ........................ ....................... .......... ......3-40
3.8.3 Driving the Cr yst a l Pins from an External Clo ck Source........... ....................... ... 3-41
3.8.4 Noise Coupling Be tween Driven Crysta l Pins and a Crys tal Oscillator......... ......3-41
3.9 Clocks and Power Manager R egister Summar y....................... ....................... .......... ......3-41
3.9.1 Clocks Mana ger Registe r Location s ..................... ....................... .......................3-41
3.9.2 Power Manager Register Su mmary............... ........................ ....................... ......3-41
4 System Integ ration Unit .............. ....................... ........................ .......... ............. .................... ........ 4-1
4.1 General-Purpo se I/O........ ....................... ........................ ....................... .......... ............. .....4 - 1
4.1.1 GPIO Operation ......... ....................... ... ........................ ....................... ..................4-1
4.1.2 GPIO Alternate Funct ion s.............. ... ....................... ........................ ... ..................4-2
4.1.3 GPIO Register De fi n iti o ns.... ... ... ........................ ....................... ....................... ..... 4-6
Intel® PX A255 Processor De veloper’s Man ual v
Contents
4.2 Interrupt Contro l ler............... ... ... ........................ ....................... ....................... .... ............ 4-20
4.2.1 Interrupt Co ntroller Op eration .................. ....................... .......... .............. ............4-20
4.2.2 Interrupt Con tr olle r Re gis te r De fi n iti o ns.......... ... ... ........................ ......................4-21
4.3 Real-Time Clock (RTC) ................. ............. ....................... ........................ .......... ............4-28
4.3.1 Real-Time Cloc k Operation.. ....................... ........................ ....................... .........4-28
4.3.2 RTC Register Definition s .. ............. ....................... ........................ ......................4-29
4.3.3 Trim Procedu re ............. ........................ .......... ............. ....................... ................4-32
4.4 Operating System (OS) Timer .................... ... .... ....................... ....................... .... ............4-34
4.4.1 Watchdog Timer Operati o n............... .... ... ....................... ........................ ............4-35
4.4.2 OS Timer Register Defin i tio ns ........................ ....................... ... ........................ .. 4-35
4.5 Pulse Width Mo dulator............ ............. ........................ ....................... ....................... ...... 4-38
4.5.1 Pulse Width Modulator Ope ration ............ ....................... ........................ ............4-38
4.5.2 Register D escriptions........... .......... ............. ........................ ....................... .........4-40
4.5.3 Pulse Width Modulator Outp ut Wave Exam ple................... ............. ...................4-43
4.6 System Integr ation Unit Re gister Summar y.................... ....................... ........................ ..4-44
4.6.1 GPIO Regist er Locations ............... .......... ............. ........................ ......................4-44
4.6.2 Interrupt Con tr olle r Re gis te r Lo ca tio ns ........... ... ....................... ........................ .. 4-45
4.6.3 Real-Time Cl ock Register L o cations............... ....................... .......... ............. ...... 4-45
4.6.4 OS Timer Register Locati o ns......... ... .... ....................... ....................... .... ............4-45
4.6.5 Pulse Width Mo dulator Register Locati ons ........... .......... .............. ......................4-46
5 DMA Controller ........... ... ... ........................ ....................... ....................... .... ..................................5-1
5.1 DMA Description.................. ... ....................... ........................ ... ....................... ..................5-1
5.1.1 DMAC Channels ............... ....................... ....................... .......... .............. ..............5-2
5.1.2 Signal Descrip tions ................. ........................ ... ....................... ........................ .... 5-2
5.1.3 DMA Channel Pr io rity Scheme ............. .......... ............. ....................... ..................5-3
5.1.4 DMA Descripto rs.................. ....................... .......... .............. ....................... ...........5-5
5.1.5 Channel State s .................... .......... ............. ........................ ....................... .......... .5-8
5.1.6 Read and Write Order............. .......... .............. ....................... ....................... ........5-9
5.1.7 Byte Transfe r Order .................... ....................... ....................... ........................ ....5-9
5.1.8 Trailing By tes ....................... ....................... ........................ .......... ............. .........5-10
5.2 Transferring D ata ....................... ........................ .......... ............. ....................... ................5-11
5.2.1 Servicing In ternal Peripherals ........... ........................ ....................... .......... .........5-11
5.2.2 Quick Referenc e for DMA Progr ammin g .............. ........................ ......................5-13
5.2.3 Servicing Companion Chip s and Exter nal Periphera ls ....................... .......... ......5-14
5.2.4 Memory-to-Mem ory Mov es................... ... ....................... .... ....................... .........5-16
5.3 DMAC Register s ........... ............. ........................ ....................... ....................... ................5-17
5.3.1 DMA Interrupt Register (DINT) ................... ........................ ....................... .........5-17
5.3.2 DMA Channel Control/Stat us Register ( DCSRx) ................... ............. ................5-17
5.3.3 DMA Request to Channel Map R e gisters (DRCMRx) .................. ............. .........5-20
5.3.4 DMA Descripto r Address R egisters (D DADRx) ..................... ....................... ...... 5-20
5.3.5 DMA Source Add ress Registe rs ................. .............. ....................... ...................5-21
5.3.6 DMA Target Ad dress Regist ers (DTADRx). .......... .............. ....................... .........5-22
5.3.7 DMA Command Reg isters (DCMDx) .............. ....................... ....................... ...... 5-23
5.4 Examples ............... .............. ....................... ....................... .......... .............. .................... .. 5-26
5.5 DMA Controller R e gister Summary ......... ............. ....................... .......... .............. ............5-28
6 Memory Controll er ................... .......... ............. ........................ ....................... .......... .......... .......... .6-1
6.1 Overview....................... ....................... ........................ ....................... ....................... ........6-1
6.2 Functional Descr ip ti o n ...................... ... ........................ ....................... ....................... ........6- 2
vi Intel® PXA255 Processor Developer’s Manual
Contents
6.2.1 SDRAM Interf a ce Overview..................... .......... ............. ....................... ............... 6-2
6.2.2 Static Memory Inter fac e / Variab le Late nc y I/O Interf ac e ................... ... ...............6-3
6.2.3 16-Bit PC C ard / Compact Fl ash Interfac e ........ ....................... ....................... ..... 6-4
6.3 Memory System Example s..................... ........................ ... ....................... ........................ . 6-4
6.4 Memory Accesses .............. ........................ ....................... ....................... .... .....................6-7
6.4.1 Reads and Writes ................... ... ........................ ....................... ....................... .... . 6-8
6.4.2 Aborts and Nonexis tent Memory ............. ... ... ........................ ....................... ... ..... 6-8
6.5 Synchronous DR AM Memory Interface ................ ....................... ....................... .......... .....6-8
6.5.1 SDRAM MDCNFG R e gister (MDCNFG............. ............. ....................... ...............6-8
6.5.2 SDRAM Mode R egister Set C onfiguration R egister (MDMR S) ................. .........6-12
6.5.3 SDRAM MDREFR Register (MDREFR) ............... ....................... .......................6-14
6.5.4 Fixed-Dela y or Return -Clock Data Latching ............ ........................ ...................6-17
6.5.5 SDRAM Memory Op tions .................... .............. ....................... ....................... ...6-18
6.5.6 SDRAM Command Overview ........... ....................... .......... .............. ...................6-27
6.5.7 SDRAM Wavefor ms ............. ....................... ....................... ........................ .........6-28
6.6 Synchronous Sta tic Memory I nterface.............. .............. ....................... ....................... ...6-32
6.6.1 Synchron ous Static Memo ry Configur ation Registe r (SXCNFG)........ ................6-32
6.6.2 Sy nc hronous Sta tic Memory Mode R eg ister Set Confi gu ration
Register (SXMRS) ..................... ........................ ....................... ....................... ...6-37
6.6.3 Synchronou s Static Memory Timing Diagrams..... ............. ........................ .........6-38
6.6.4 Non-SDRAM Timi ng SXMEM Operati on .............. ....................... .......................6-39
6.7 Asynchronous St a tic Memory ................. ........................ .......... ............. ....................... ... 6 -42
6.7.1 Static Memory Inter fac e............. .... ....................... ... ........................ ...................6-42
6.7.2 Asynchrono us Static Memor y Control Re gisters (MSCx)...................... .......... ...6 -44
6.7.3 ROM Interf ace ..................... ....................... .......... ............. ........................ ......... 6-48
6.7.4 SRAM Interface Overv i ew ................ ... ........................ ....................... ... .............6 -51
6.7.5 Variable L atency I/O (VLIO) Interface Overview...... .......... .............. ...................6-53
6.7.6 FLASH Memory Interface .................... .............. ....................... .......... ............. ... 6-56
6.8 16-Bit PC Ca r d/Compact Flash Interfac e ... ............. ....................... ........................ .........6-58
6.8.1 Expansion Memory Timing Co nfiguration Register .................. .......... ............. ... 6-58
6.8.2 Expansion Memory Configura tion Register (MECR) ............. .......... ............. ...... 6-61
6.8.3 16-Bit PC C ard Overview..... .......... ............. ....................... ........................ ......... 6-62
6.8.4 External L ogic for 16-Bit PC Car d Implementatio n ................... ....................... ... 6-64
6.8.5 Expansion Card Interfa ce Timing Dia grams and Paramet ers ..... .............. ......... 6-67
6.9 Companion Chip Int erfa ce................... ... ........................ ....................... ... .......................6-68
6.9.1 Alternate Bus Master Mode .............. ....................... .......... .............. ...................6-70
6.10 Options and Settings for Boot Memory................. ....................... ....................... .......... ...6 -72
6.10.1 Alternate Booting ....................... ........................ ....................... .......... ............. ... 6-72
6.10.2 Boot Time Defaults ................. ... .... ....................... ....................... .... ...................6-72
6.10.3 Memory Interf ace Reset a nd Initializ ation.......... ............. ....................... .............6 -76
6.11 Hardware, Wat c hdog, or Sleep Reset Op eration .............. .......... ............. .......................6-77
6.12 GPIO Reset Pr ocedure.............. ....................... ........................ ....................... .......... ......6 -79
6.13 Memory Contro ller Register Summary .................... ............. ........................ ...................6-79
7 LCD Control ler.................. .......... ............. ........................ ....................... .......... ............. ...............7-1
7.1 Overview............. ............. ....................... ........................ .......... ............. .................... ........ 7-1
7.1.1 Features. ............. ....................... ........................ ....................... .......... ............. ..... 7-2
7.1.2 Pin Desc riptions............... .............. ....................... ....................... .......... .............. . 7-4
7.2 LCD Control ler Operatio n ............. .......... .............. ....................... ....................... .......... .....7-4
7.2.1 Enabling t h e Controller .............. .............. ....................... ....................... ...............7-4
Intel® PX A255 Processor De veloper’s Man ual vii
Contents
7.2.2 Disabling th e Controlle r ........................ ....................... .......... ............. ..................7-5
7.2.3 Resetting t he Controller .............. ....................... .......... ............. ........................ .... 7-5
7.3 Detailed Module Descriptio ns ..................... ....................... ........................ .......... ............. . 7-5
7.3.1 Input FIFOs................... ........................ .......... ............. ....................... ..................7-5
7.3.2 Lookup Palet te .............. ........................ ....................... ....................... .......... ........7-6
7.3.3 Temporal Modulate d Ener gy Distr i buti o n (TMED ) Dith e rin g.. ... .... ....................... . 7-6
7.3.4 Output FIFOs ................ .... ....................... ... ........................ ....................... ...........7-8
7.3.5 LCD Contr oller Pin Us age .......... ............. ....................... ........................ ..............7-8
7.3.6 DMA .............. ....................... .......... ............. ........................ ....................... .......... .7-9
7.4 LCD External Pa lette and Fr ame Buffers .................... ............. ....................... .......... ......7-10
7.4.1 External Pa lette Buffer................... ............. ........................ ....................... .........7-10
7.4.2 External Fra me Buffer............. ........................ .......... ............. ....................... ...... 7-11
7.5 Functional Timing ................... ... ........................ ....................... ....................... .... ............7- 14
7.6 Register Descrip ti o ns.... ... .... ....................... ....................... ........................ ......................7-17
7.6.1 LCD Contr oller Cont rol Register 0 (LCCR0)................... .......... .............. ............7-18
7.6.2 LCD Contr oller Cont rol Register 1 (LCCR1)................... .......... .............. ............7-24
7.6.3 LCD Contr oller Cont rol Register 2 (LCCR2)................... .......... .............. ............7-26
7.6.4 LCD Contr oller Cont rol Register 3 (LCCR3)................... .......... .............. ............7-28
7.6.5 LCD Contr oller DMA ................... ....................... ....................... .......... .............. .. 7-32
7.6.6 LCD DMA Fram e Branch Reg isters (FBRx) ....................... ....................... .........7-37
7.6.7 LCD Contr oller Status R e gister (LCSR).......... ....................... ....................... ...... 7-38
7.6.8 LCD Controlle r In te rrup t ID Re gis ter (L IID R) ............... ....................... ................7-41
7.6.9 TMED RGB Seed Register (TRG BR) ....................... ....................... ...................7-42
7.6.10 TMED Control Register ( TCR) .............. ....................... ....................... ................7-43
7.7 LCD Controll er Register Su mmary .................... ....................... ....................... ................7-44
8 Synchronous Seri al Port Co nt ro ll er .................... ... ... ........................ ....................... .....................8-1
8.1 Overview....................... ....................... ........................ ....................... ....................... ........8-1
8.2 Signal Descri ption ...................... ........................ .......... ............. ....................... ..................8-1
8.2.1 External In terface to Syn chronous Ser ial Peripheral s .... ........................ ..............8-1
8.3 Functional Descr ip ti o n ...................... ... ........................ ....................... ....................... ........8- 2
8.3.1 Data Transfer................ .............. ....................... ....................... ........................ ....8-2
8.4 Data Formats ............. .......... ............. ....................... .......... .............. ....................... ...........8-2
8.4.1 Serial Data Formats for Transfer to/f r om Peripherals ............... ........................ ....8-2
8.4.2 Parallel Dat a Formats for FIFO Storage ............... ........................ ....................... . 8-6
8.5 FIFO Operation a nd Data Transfers .................. ....................... ....................... ..................8-7
8.5.1 Using Programmed I/O Data Tran sfers ....................... ....................... ..................8-7
8.5.2 Using DMA Data Transfers................... ... ....................... ........................ ... ...........8-7
8.6 Baud-Rate Generati on............... .... ... ....................... ........................ ....................... ... ........8-7
8.7 SSP Serial Port R egisters.................... .............. ....................... ....................... .......... ........8-8
8.7.1 SSP Control R e gister 0 (SSCR0) ................... ....................... ....................... ........8 -8
8.7.2 SSP Control R e gister 1 (SSCR1) ................... ....................... ....................... ...... 8-11
8.7.3 SSP Data R egister (SSDR ) .... ........................ ....................... ....................... ...... 8-15
8.7.4 SSP Status Re gister (SSSR)................... ............. ........................ ......................8-16
8.8 SSP Controller R egister Summary ....................... .......... ............. ........................ .......... ..8-19
9I
2
C Bus Inter face Unit................. ........................ ....................... ....................... ............................ 9-1
9.1 Overview....................... ....................... ........................ ....................... ....................... ........9-1
9.2 Signal Descri ption ...................... ........................ .......... ............. ....................... ..................9-1
9.3 Functional Descr ip ti o n ...................... ... ........................ ....................... ....................... ........9- 1
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9.3.1 Operational Blocks........ .......... ............. ........................ ....................... .......... ........9-3
9.3.2 I2C Bus In terface Modes ................. ....................... .......... .............. .....................9-3
9.3.3 Start and Stop Bus Stat es ...... ....................... ........................ .......... ............. ........ 9-4
9.4 I2C Bus Oper ation ........... ....................... ........................ .......... ............. ....................... ..... 9 -7
9.4.1 Serial Cl o ck Line (SCL) Generati on............ ............. ........................ .....................9-7
9.4.2 Data and Ad dressing Mana gement ............ ............. ........................ .....................9-7
9.4.3 I2C Acknow ledge.................... .......... ............. ........................ ....................... ........ 9-8
9.4.4 Arbitratio n .................. .......... ............. ....................... ........................ .......... ...........9-9
9.4.5 Master Oper ations ........... ........................ .......... ............. ....................... .............9 -12
9.4.6 Slave Operatio ns ................. ... ....................... ........................ ... ....................... ... 9-14
9.4.7 General Call Addre ss..................... ... ....................... ........................ ...................9-16
9.5 Slave Mode Pro gramming Examp les ..... ........................ ....................... .......... ............. ... 9-18
9.5.1 Initiali ze Unit .................... ........................ ....................... ....................... .............9 -18
9.5.2 Write n Byt e s as a Slave................ ....................... ....................... .......................9-18
9.5.3 Read n Byte s as a Slave ............... .......... ............. ....................... .......................9-18
9.6 Master Programmi ng Examples ................. ....................... ....................... .......... .............9-19
9.6.1 Initiali ze Unit .................... ........................ ....................... ....................... .............9 -19
9.6.2 Write 1 Byt e as a Maste r ........ ....................... ........................ .......... ............. ...... 9-19
9.6.3 Read 1 Byte as a Master .................. .......... ............. ........................ ...................9-20
9.6.4 Write 2 Byt es and Repeate d Start Rea d 1 Byte as a Master....... .......................9-20
9.6.5 Read 2 Byte s as a Master - Send STOP U sing the Abort .................. ................9-21
9.7 Glitch Suppressio n Logi c ........ ... ....................... ........................ ....................... ... .............9 -21
9.8 Reset Conditi ons .................... ....................... ....................... .......... .............. ...................9 -2 1
9.9 Register Defi nitions... .............. ....................... ....................... ........................ ...................9-22
9.9.1 I2C Bus Monitor Regis te r (IB MR) .................. ........................ ... ....................... ... 9-22
9.9.2 I2C Data Buffer Regist er (IDBR)....... .......... ............. ........................ ...................9-22
9.9.3 I2C Contr ol Register (ICR)......... ........................ ....................... ....................... ... 9-23
9.9.4 I2C Status Register (I SR) ....... ....................... .......... .............. ....................... ...... 9-25
9.9.5 I2C Slave A d dress Register (ISAR)............... ........................ ....................... ......9-27
10 UARTs .......... ............. ........................ ....................... .......... ............. ........................ ...................10-1
10.1 Feature List............ ... .... ....................... ....................... .... ....................... .................... ...... 10-1
10.2 Overview............. ............. ....................... .......... .............. ....................... .................... ...... 10-2
10.2.1 Full Function UART ................ ... ........................ ... ....................... .......................10-2
10.2.2 Bluetooth UART...................... ....................... ........................ ....................... ......10-2
10.2.3 Standard UA RT ............... .......... .............. ....................... ....................... .............1 0-2
10.2.4 Compatibility with 16550.............................................. .......... ............. ................10-2
10.3 Signal Descrip ti o ns.................... ... .... ....................... ....................... ........................ ......... 1 0-3
10.4 UART Operat ional Descrip tion ................... .......... ............. ....................... .......................10-4
10.4.1 Reset .................. ....................... ........................ .......... ............. ....................... ... 10-5
10.4.2 Internal Regis ter Descript i ons.... ........................ ... ....................... .......................10-5
10.4.3 FIFO Interrupt Mod e Opera ti o n .................. ....................... ........................ ... .... 10-21
10.4.4 FIFO Polled Mode Operati on ...................... .......... ............. ........................ .......10-22
10.4.5 DMA Requests. ... ... ........................ ....................... ....................... .....................10-22
10.4.6 Slow Infrared Asy nc hron o us Inte rfa ce........... .... ... ....................... .....................10-23
10.5 UART Regist er Summary .................... ............. ........................ ....................... ..............10-26
10.5.1 UART Reg ister Differ ences ................. .............. ....................... ....................... . 10-28
11 Fast Infrar ed Communication Port........ ............. ........................ ....................... .......... ............. ...11 -1
11.1 Signal Descrip ti o n............ ... ........................ ... ....................... ........................ ...................11-1
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11.2 FICP Operatio n ............. ....................... ........................ .......... ............. ....................... ...... 11 -1
11.2.1 4PPM Modulation ................... .............. ....................... ....................... .......... ......11-2
11.2.2 Frame Format ............... ........................ ....................... ....................... .......... ......11-3
11.2.3 Address Field................ .............. ....................... ....................... ........................ ..11-3
11.2.4 Control Field ................. .... ... ....................... ........................ ....................... ... ...... 11-3
11.2.5 Data Field ..................... .......... .............. ....................... ....................... ................11-3
11.2.6 CRC Field ............... ....................... ....................... .......... .............. ......................11-4
11.2.7 Baud Rate Generation ............ .... ....................... ....................... ........................ ..11-4
11.2.8 Receive Operatio n ............... ....................... .... ....................... ....................... ...... 11-4
11.2.9 Transmit Ope ration ................. ........................ ....................... .......... ............. ...... 11-5
11.2.10 Transmit and Receive FIFOs ............ ........................ ....................... ...................11-6
11.2.11 Traili n g or Error Bytes in the Receive FIFO.................... ........................ .......... ..11-7
11.3 FICP Registe r Definitio n s .................... ........................ ....................... ....................... ...... 11-7
11.3.1 FICP Control Regis te r 0 (ICCR0) ... ....................... .... ....................... ...................11-8
11.3.2 FICP Control Regis te r 1 (ICCR1) ... ....................... .... ....................... .................11-10
11.3.3 FICP Control Regis te r 2 (ICCR2) ... ....................... .... ....................... .................11-11
11.3.4 FICP Data Re g ister (ICDR)............ ....................... ........................ ....................11-12
11.3.5 FICP Status Register 0 (ICSR0) .............. .......... ............. ........................ ..........1 1-13
11.3.6 FICP Status Register 1 (ICSR1) .............. .......... ............. ........................ ..........1 1-15
11.4 FICP Registe r Summary...................... .......... .............. ....................... ....................... .... 11-16
12 USB Device Control ler...... .... ... ....................... ........................ ....................... .............................12-1
12.1 USB Overview ..................... ....................... ....................... .... ....................... ...................12-1
12.2 Device Config uration ................. .............. ....................... ....................... .......... .............. ..12-2
12.3 USB Protocol ............. ... ... ........................ ....................... ....................... .... .................... .. 12-2
12.3.1 Signalling L e vels ........... ........................ ....................... .......... ............. ................12-3
12.3.2 Bit Encoding........ .......... .............. ....................... ....................... .......... .............. .. 12-3
12.3.3 Field Formats.................... ... ... ........................ ....................... ....................... .... .. 12-4
12.3.4 Packet Forma ts.................... ....................... ........................ ....................... .........12-5
12.3.5 Transaction Formats ...................... ....................... ........................ .......... ............12-6
12.3.6 UDC Device Requests...................... ........................ ....................... .......... .........12-8
12.3.7 Configuratio n .......... ............. ....................... ........................ ....................... .........12-9
12.4 UDC Hardwa re Connection ................. .......... .............. ....................... ....................... .... 12-10
12.4.1 Self-Powered De vic e .............. .... ....................... ....................... ........................12-10
12.4.2 Bus-Powered De vic es ................... ... ........................ ... ....................... ..............12-12
12.5 UDC Operation .................... ....................... .......... ............. ........................ ....................12-1 2
12.5.1 Case 1: EP0 Control Read ..... ........................ ....................... ... ........................12-12
12.5.2 Case 2: EP0 Co ntrol Read with a Premat ure Status St age.................... ..........12-13
12.5.3 Case 3: EP0 C ont rol Write Wi th or W ithout a Pre m at ur e Status
Stage ........ ........................ ....................... ....................... ........................ ..........12-14
12.5.4 Case 4: EP0 No Data Command.................... ....................... .......... ............. .... 12-15
12.5.5 Case 5: EP1 Data Transmit (BULK-I N ).... ... .... ....................... ....................... .... 12-15
12.5.6 Case 6: EP2 Da ta Receive ( BULK-OUT).... .......... .............. ....................... .......1 2-16
12.5.7 Case 7: EP3 Data Transmit (ISOCHR ON OUS- IN) ................ ... ........................12-17
12.5.8 Case 8: EP4 Data Receiv e (ISOCHRONOU S-OUT) ............. .......... ............. .... 12-18
12.5.9 Case 9: EP5 Data Transmit (INTER RUPT-IN) ......... ... ....................... ..............12-20
12.5.10 Case 10: RESET Inter rupt ....................... ....................... ........................ ..........12-20
12.5.11 Case 11: SUSPEND Int errupt.................. ....................... ........................ ..........12-21
12.5.12 Case 12: RESUME Inte rrupt................. .......... ............. ....................... ..............12-21
12.6 UDC Register Definition s ............... ....................... ....................... ........................ ..........12-21
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12.6.1 UDC Control Re gis te r (U DCC R).... ... .................... ... .... ....................... ..............12-22
12.6.2 UDC Contr o l Function Register (UDCCFR)....... .......... .......... ............. ..............12-24
12.6.3 UDC End point 0 Con trol/Status Register (U DCCS0) .................. .............. ....... 12-25
12.6.4 UDC Endpoint x Cont ro l/St atus Register (UDCCS1/6/11)..... ... ....................... . 12-27
12.6.5 UDC Endpoint x Cont ro l/St atus Register (UDCCS2/7/12)..... ... ....................... . 12-29
12.6.6 UDC Endpoint x Cont ro l/St atus Register (UDCCS3/8/13)..... ... ....................... . 12-31
12.6.7 UDC Endpoint x Cont ro l/St atus Register (UDCCS4/9/14)..... ... ....................... . 12-32
12.6.8 UDC Endpoint x Cont ro l/ St at us Re gis t e r (UDCC S5/10/15)................... ........... 12-34
12.6.9 UDC Inte rrupt Contr o l Register 0 (UICR0) .............. .......... .............. .................12-36
12.6.10 UDC Interrupt Control Register 1 ( UICR1) ..................... ....................... ........... 12-38
12.6.11 U DC Status/Interrupt Re gister 0 (US IR0) ................ ........................ .................12-39
12.6.12 U DC Status/Interrupt Re gister 1 (US IR1) ................ ........................ .................12-41
12.6.13 U DC Frame Number High Regist e r (UFNHR) ............. ....................... .......... ....12-42
12.6.14 U DC Frame Number Low Regist er (UFNLR) .................... ........................ .......12-44
12.6.15 UDC Byte Count Register x (UBCR2/4/7 /9/12/14) ................... ....................... . 12-44
12.6.16 UDC Endpoint 0 Data Regi ster (UDDR0 ) ................ .............. ....................... .... 12-45
12.6.17 UDC Endpoint x Data Reg ister (UDD R1/6/11) ............ ....................... ..............12-46
12.6.18 UDC Endpoint x Data Reg ister (UDD R2/7/12) ............ ....................... ..............12-46
12.6.19 UDC Endpoint x Data Reg ister (UDD R3/8/13) ............ ....................... ..............12-47
12.6.20 UDC Endpoint x Data Reg ister (UDD R4/9/14) ............ ....................... ..............12-47
12.6.21 UDC Endpoint x Data Reg ister (UDD R5/10/15) .................... .......... ............. .... 12-48
12.7 USB Device Co ntroller Re gister Summary................. .............. ....................... .............. 12-48
13 AC’97 Controll er Unit............... ....................... ....................... ........................ .................... ......... 13-1
13.1 Overview............. ............. ....................... .......... .............. ....................... .................... ...... 13-1
13.2 Feature List............ ... .... ....................... ....................... .... ....................... .................... ...... 13-1
13.3 Signal Descrip ti o n............ ... ........................ ... ....................... ........................ ...................13-2
13.3.1 Signal Con figuration St eps ............... ....................... ........................ ...................13-2
13.3.2 Example AC-l ink ........ ....................... ....................... ........................ .......... .........13-2
13.4 AC-link Dig ital Serial I n terface Protocol................ ............. ....................... .......................13-3
13.4.1 AC-link Au dio Output Frame (SDATA_ OUT) ..................... .......... .............. ......... 13-4
13.4.2 AC-link Au dio Input Fr ame (SDATA_IN )............... ....................... .......... .............13-8
13.5 AC-link Low Power Mode ................. ....................... ....................... ........................ ... .... 13-12
13.5.1 Powering Down the AC-l in k..................... ....................... ....................... ........... 13-12
13.5.2 Waking up t h e AC-link ................... .......... ............. ....................... .....................13-13
13.6 ACUNIT Oper ation........ ............. ....................... ........................ .......... ............. ..............13-14
13.6.1 Initiali zation ............ .............. ....................... .......... ............. ........................ ....... 13-15
13.6.2 Trailing bytes ................ ............. ........................ ....................... ....................... . 13-17
13.6.3 Operatio nal Flow for Ac cessing CODEC Register s ........... ........................ ....... 13-17
13.7 Clocks and Sampling Fre que nc i es ................ ... .... ....................... ....................... ........... 13-17
13.8 Functional D escription .................. ........................ ....................... ....................... .......... . 13-18
13.8.1 FIFOs.................. ....................... ........................ .......... ............. ....................... . 13-18
13.8.2 Interrupts... ....................... .......... .............. ....................... ....................... ........... 13-19
13.8.3 Registers... .......... ............. ........................ ....................... ....................... ........... 13-19
13.9 AC’97 Regist er Summary .................... ............. ........................ ....................... ..............13-35
14 Inter-Integ rated-Circui t Sound (I2S) Controller............ ........................ ....................... .......... ......14-1
14.1 Overview............. ............. ....................... .......... .............. ....................... .................... ...... 14-1
14.2 Signal Descrip ti o ns.................... ... .... ....................... ....................... ........................ ......... 1 4-2
14.3 Controller O peration .................. ....................... ........................ ....................... ................1 4- 3
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14.3.1 Initializat io n ................... .............. ....................... .......... ............. ........................ .. 14-3
14.3.2 Disabling a nd Enabling Audio Replay......... .............. ....................... ...................14-4
14.3.3 Disabling a n d Enabling Audio Record ............ .......... ............. ....................... ...... 14-4
14.3.4 Transmit FIFO Errors ........... ....................... ........................ ....................... .........14-5
14.3.5 Receive FIFO Errors................... ... ... ........................ ....................... ...................14-5
14.3.6 Trailing By tes ....................... ....................... ........................ .......... ............. .........14-5
14.4 Serial Audio C locks and Sampli ng Frequenci es ............. ....................... .......... .............. .. 14-5
14.5 Data Formats ............. ....................... ....................... .......... .............. ....................... .........14-6
14.5.1 FIFO and Memory Format ................ .............. ....................... ....................... ......14-6
14.5.2 I2S and MSB-Justified Serial Audi o Format s............ ....................... ...................14-6
14.6 Registers.......... .......... ............. ....................... ........................ ....................... .......... ....... ..14-8
14.6.1 Serial Audio Controller Global Contr ol Registe r (SACR0) .................. ................14-8
14.6.2 Serial Au dio Contr oller I2S/ MSB-Justi fied Contro l Register
(SACR1) ....... ....................... ....................... ........................ .......... ............. .......1 4-10
14.6.3 Serial Audio Con troller I2S/MSB-Ju stified Status Regi ster
(SASR0).............. .......... .............. ....................... ....................... .......... ..............14-11
14.6.4 Serial Audio Clock Divider Register ( SADIV) ............ ....................... .................14-12
14.6.5 Serial Audio Interrupt Clear Regist er (SAICR)............. .......... ............. ..............14-13
14.6.6 Serial Audio Interrupt Mas k Register ( SAIMR) ...................... ....................... ....14-14
14.6.7 Serial Audio Data Registe r (SADR) ................ ............. ....................... ..............14-14
14.7 Interrupts.......... ....................... .......... ............. ........................ ....................... .......... .......14-15
14.8 I
2
S Controller Register Su mmary ........ .......... .............. ....................... ....................... ....14-15
15 MultiMediaCard Controller................. ............. ........................ ....................... ....................... ...... 15-1
15.1 Overview.................... ............. ....................... ........................ .......... ............. ...................15-1
15.2 MMC Controller F unctional D escription ................ ....................... ........................ ............15-4
15.2.1 Signal Descrip ti o n................... .... ... ....................... ........................ ......................15-6
15.2.2 MMC Controlle r Reset ................ ....................... .......... ............. ........................ .. 15-6
15.2.3 Card Initializa tio n Sequence ................. ... ....................... .... ....................... .........15-6
15.2.4 MMC and SPI Mode s..................... ....................... .......... .............. ......................15-6
15.2.5 Error Detect ion .............. .......... .............. ....................... ....................... ................15-8
15.2.6 Interrupts.......... .......... ............. ........................ ....................... ....................... ......15-8
15.2.7 Clock Contr ol .................... ............. ....................... ........................ ......................15-9
15.2.8 Data FIFOs ............. .......... ............. ....................... ........................ .......... ..........15-10
15.3 Card Communicat ion Protocol................. ............. ....................... .......... .............. ..........15-12
15.3.1 Basic, No Da ta, Command and R e sponse Sequence .............. ........................15-13
15.3.2 Data Transfer................ .............. ....................... ....................... ........................15-13
15.3.3 Busy Sequenc e.................... ....................... .......... .............. ....................... .......1 5-16
15.3.4 SPI Functio nality ........... ........................ ....................... .......... ............. ..............15-17
15.4 MultiMediaCard Controller O peration ...................... ........................ .......... ............. .......1 5-17
15.4.1 Start and Stop Clock................... ... ... ........................ ....................... ... ..............15-17
15.4.2 Initialize................... ....................... .......... ............. ........................ ....................15-17
15.4.3 Enabling SPI Mode ................. .............. ....................... ....................... .......... ....15-17
15.4.4 No Data Co mmand and Resp onse Sequence.......... .......... ............. .................15-18
15.4.5 Erase ........ ........................ ....................... ....................... .......... .............. ..........15-18
15.4.6 Single Data Block Wri te .............. ... ....................... .... ....................... .................15-18
15.4.7 Single Block Read ..... ....................... ........................ ....................... ... ..............15-19
15.4.8 Multiple Blo ck Write ................ ........................ ....................... ....................... ....15-20
15.4.9 Multiple Blo ck Read ................ .............. ....................... ....................... .......... ....15-20
15.4.10 Stream Write.............. ... ........................ ....................... ... ........................ ..........1 5-21
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15.4.11 Stream Read................. ............. ........................ ....................... .......... ............. . 15-21
15.5 MMC Controlle r Registers ............ .............. ....................... ....................... .....................15-22
15.5.1 MMC_STRPCL Regis ter.. .... ... ....................... ........................ ... ....................... . 15-22
15.5.2 MMC_Status R egister (MMC_ STAT) ...... ....................... ....................... ........... 15-23
15.5.3 MMC_CLKRT R egister (MMC_CL KRT) ............... ....................... .....................15-24
15.5.4 MMC_SPI Register (MMC_SPI) ................. ....................... ........................ ... .... 15-25
15.5.5 MMC_CMDAT Registe r (MMC_CMD AT ) .................... ... ....................... ........... 15-26
15.5.6 MMC_RESTO Regi ster (MMC_RESTO ) ................. ........................ .................15-27
15.5.7 MMC_RDTO R egister (MMC_ RDTO) ..... ....................... ....................... ........... 15-28
15.5.8 MMC_BLKLEN Re gister (MMC_BLK LEN) .............. ........................ .................15-29
15.5.9 MMC_NOB Registe r (MMC_NOB) .................... .......... ............. ....................... . 15-29
15.5.10 MMC_PRTBUF Register (MMC_PRTBUF ) .................... ....................... .......... . 15-30
15.5.11 MMC_I_MASK Register (MMC_I_MAS K) ......... ....................... ....................... . 15-30
15.5.12 MMC_I_REG Register (MMC_I_REG) .................... ........................ .......... .......15-31
15.5.13 MMC_CMD Register (MMC_CMD) ......... ... ....................... ........................ ... .... 15-33
15.5.14 MMC_ARGH Register (MMC_ARGH) ............... ....................... ....................... . 15-35
15.5.15 MMC_ARGL Register (MMC_ARGL) ............ .... ... ....................... .....................15-35
15.5.16 MMC_RES FIFO ........ ... ....................... .... ....................... ....................... .... ....... 15-36
15.5.17 MMC_RXFIFO FIFO ............ .......... ............. ....................... .......... .............. ....... 15-36
15.5.18 MMC_TXFIFO FIFO .. ... ... ........................ ....................... ... ........................ ....... 15-37
15.6 MultiMediaCar d Controller Register Su mmary ............... ....................... ....................... . 15-37
16 Network SSP Serial Port ............... ........................ ....................... ... ........................ ...................16-1
16.1 Overview............. ............. ....................... .......... .............. ....................... ....................... ... 16-1
16.2 Features.... ............. ....................... ........................ ....................... .......... ............. .............16-1
16.3 Signal Descrip ti o n............ ... ........................ ... ....................... ........................ ...................16-2
16.4 Operation ...................... ....................... ....................... .......... .............. ...................... ....... 16-2
16.4.1 Processor a nd DMA FIFO Ac cess................. .......... .............. ....................... ...... 16-2
16.4.2 Trailing Bytes in the Receive FI FO .................... ............. ....................... .............16-3
16.4.3 Data Forma ts ................ .......... ............. ........................ ....................... .......... ......16-3
16.4.4 Hi-Z on S SPTXD........... ............. ........................ ....................... .......... ............. . 16-13
16.4.5 FIFO Operation............. ... ........................ ....................... ... ........................ ....... 16-17
16.4.6 Baud-Rate Ge neration............... .............. ....................... ....................... ........... 16-17
16.5 Register De scriptions.... ....................... ....................... ........................ ....................... .... 16-18
16.5.1 SSP Control Re gister 0 (SSC R0) ............... ....................... .......... .............. ....... 16-18
16.5.2 SSP Control Re gister 1 (SSC R1) ............... ....................... .......... .............. ....... 16-20
16.5.3 SSP Programmab le Serial Pr otocol Regist er (SSPSP)................... .......... .......16-22
16.5.4 SSP Time Out Re gister (SST O) ................. ....................... .......... .............. ....... 16-24
16.5.5 SSP Interrup t Test Register (SSITR)................. ............. ....................... ........... 16-24
16.5.6 SSP Status Re gister (SSSR)............ .......... ............. ........................ .......... .......16-25
16.5.7 SSP Data Re gister (SSDR) .............. ............. ........................ .......... ............. .... 16-28
16.6 Network SSP Serial Port Registe r Summary........... ... ........................ ... ....................... .16-29
17 Hardware UART ............... .......... ............. ........................ ....................... ....................... .......... ... 17-1
17.1 Overview............. ............. ....................... .......... .............. ....................... .................... ...... 17-1
17.2 Features.... ............. ....................... ........................ ....................... .......... ............. .............17-1
17.3 Signal Descrip ti o ns.................... ... .... ....................... ....................... ........................ ......... 1 7-3
17.4 Operation ...................... ....................... ....................... .......... .............. ...................... ....... 17-3
17.4.1 Reset .................. ....................... ........................ .......... ............. ....................... ... 17-4
17.4.2 FIFO Operation............. ... ........................ ....................... ... ........................ ......... 17-4
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17.4.3 Autoflow Contro l ..................... ........................ ... ....................... ........................ .. 17-7
17.4.4 Auto-Baud-Ra te Detection.................... ....................... ....................... ................17-7
17.4.5 Slow Infrar ed Asynchronou s Interface.................. .............. ....................... .........17-8
17.5 Register Descri p tio ns.... ... ........................ ....................... ....................... ........................17-10
17.5.1 Receive Buf fer Register ( RBR) ............. ....................... .......... ............. ..............17-10
17.5.2 Transmit Hol ding Registe r (THR)...... ........................ ....................... .................17-10
17.5.3 Divisor L atch Registe rs (DLL and DLH)................ .......... .............. ....................17-10
17.5.4 Interrupt En able Registe r (IER) ..... ....................... .......... .............. ....................17-11
17.5.5 Interrupt Ide nti fi ca tio n Re gis te r (II R).................. ... .... ....................... .................17-13
17.5.6 FIFO Control Regis te r (FCR)................... ... ........................ ....................... .......1 7-15
17.5.7 Receive FIFO Occupa ncy Reg ist e r (FOR) .................. ....................... ..............17-16
17.5.8 Auto-Baud Co ntrol Regist e r (ABR) ................. .......... ............. ....................... .... 17-17
17.5.9 Auto-Baud Count Re gis ter (AC R)................... ... ... ........................ ....................17-17
17.5.10 Line C ontrol Reg ister (LCR). .......... ............. ........................ ....................... .......1 7-18
17.5.11 Line S tatus Registe r (LSR) ................... ....................... ....................... ..............17-19
17.5.12 Modem Contr ol Re gis te r (MC R) ..................... ... ....................... ........................17-21
17.5.13 Modem St a tus Register (MSR) ....................... ....................... ....................... .... 17-23
17.5.14 Scratc h pad Register (SCR) .............. .............. ....................... ....................... .... 17-24
17.5.15 Infra red Selection R e gister (ISR) ............. ............. ........................ ....................17-24
17.6 Hardware UART Regis ter Summary........... ... .... ....................... ....................... ..............17-25
Figures
2-1 Block Diag ram ..... ........................ ....................... ....................... .......... .............. .................... .... 2-2
2-2 Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF ............. ............. ................2-19
2-3 Memory Map (Part Two) — From 0x0000_0000 t o 0x7FFF FFFF ................ .............. ............2-20
3-1 Clocks Manager Block Di agr am ............... ... ........................ ... ....................... ........................ ....3-3
4-1 General-Purpo se I/O Blo ck Diagram .................. ............. ........................ ....................... ...........4-2
4-2 Interrupt Con tr olle r Blo ck Di a gram .............. .... ....................... ....................... ........................ ..4-21
4-3 PWMn Block Diagram.... .... ....................... ....................... .... ....................... ....................... ......4-39
4-4 Basic Pulse W idth Waveform ................ ....................... ....................... .......... .............. ............4-43
5-1 DMAC Block D iagram..................... ....................... ........................ ....................... .................... . 5-1
5-2 DREQ timing r equirements............. ............. ........................ ....................... .......... ............. ........5-3
5-3 No-Descrip to r Fetc h Mode Chann el Sta te............. .... ....................... ....................... ..................5-6
5-4 Descriptor F etch Mode Cha nnel State...... ............. ........................ ....................... .....................5-8
5-5 Little Endi an Transfers............. ........................ .......... ............. ....................... .................... ......5-10
6-1 General Memory Interface Con figuration..... .............. ....................... ....................... .......... ........6-2
6-2 SDRAM Memory Syste m Example .............. .............. ....................... ....................... .......... ........6-5
6-3 Static Memory System Exam ple............... ....................... ........................ ... ....................... ........6-6
6-4 External to Internal Ad dress Mapping Options ....................... .......... ............. ........................ .. 6-19
6-5 Basic SDRAM Timin g Parameters..... .......... .............. ....................... .......... ............. ................6-29
6-6 SDRAM_Read_dif fbank_diffr ow .................. .............. ....................... ....................... ................6-29
6-7 SDRAM_read_sameb ank_diffrow ............... .............. ....................... ....................... .......... ......6-30
6-8 SDRAM_read_sameba n k_samerow ........... .......... .............. ....................... ....................... ......6-30
6-9 SDRAM_write .................... ....................... .......... ............. ........................ ....................... .........6-31
6-10 SDRAM 4-Beat Read/ 4-Beat Wr ite To Dif fere nt Parti ti ons........... ....................... ...................6-31
6-11 SDRAM 4-Beat Write / 4-Write Same Bank, Same Row ........... .... ....................... ...................6-32
6-12 SMROM Read Timing Diagra m Hal f- Memo ry Cl ock Fr eque n cy ................... ........................ .. 6-39
6-13 Burst-of-Ei ght Synchronous F lash Timing Diag ram (non-divide -by-2 mode) .................... ......6-41
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6-14 Flash Memo ry Reset Usin g State Mach ine .................. ............. ....................... .......................6-42
6-15 Flash Memory Reset Lo g ic if Watchdog Reset is Not Nece ssary ................. ....................... ... 6-42
6-16 MSC0/1/2.......... ....................... ....................... ........................ .......... ............. .................... ...... 6-45
6-17 32-Bi t B urst-of-Eig ht ROM or Flash R ead Timing Diagr am (MSC0[R DF ] = 4,
MSC0[RDN] = 1, MSC0[RRR] = 1).............. ....................... ........................ .......... ............. ...... 6-49
6-18 Eigh t -B eat Burst Re ad from 16-Bit Bur st-of-Fou r R OM or Flash
(MSC0[RDF] = 4, MSC0[RDN] = 1, MSC0[RRR] = 0) .................. ........................ ...................6-50
6-19 32-Bi t Non-burst RO M, SRAM, or F la s h Read Timin g Di a gram - Four Da ta
Beats (MSC0[RD F] = 4, MSC0[R RR] = 1)............. ....................... ........................ ...................6-51
6-20 32-Bi t S RAM Write Tim ing Diagram (4 -b eat Burst (MS C0[RDN] = 2,
MSC0[RRR] = 1)..... .............. ....................... ....................... ........................ ....................... ......6-52
6-21 32-Bit Variable Lat ency I/O Read Tim in g (Burst-of -F o ur, One Wait C yc l e P er
Beat) (MSC0[R DF] = 2, MSC0[RDN ] = 2, MSC0[RRR] = 1) .................. ........................ .........6-54
6-22 32-Bit Variable Lat ency I/O Write T i m i ng ( Burst-of-F our, Variabl e Wa it Cycles
Per Beat) ....................... ....................... .......... .............. ....................... ....................... .............6-55
6-23 Asynchron ous 32-Bit Fl ash Write Timi ng Diagram (2 Writes) ............. ....................... .............6 -57
6-24 MCMEM1............. ....................... .......... .............. ....................... ....................... .......... .......... ... 6-58
6-25 MCATT1 ..................... .......... ............. ....................... ........................ ....................... .......... ...... 6-58
6-26 16-Bit PC C a rd Memory Map ............ ............. ........................ ....................... .......... ............. ...6-62
6-27 Expansion Card Extern al Logic for a One-Socke t Configurati on................ ............. ................6-65
6-28 Expansion Card Extern al Logic for a Two-Socke t Configurati on................ ............. ................6-66
6-29 16-Bit PC Card Memory or I /O 16-Bit (H alf-word) Acce ss ................ .......... ............. ................6-67
6-30 16-Bit PC Card I/O 16- Bit Access t o 8-Bit Device ..................... ....................... .......................6-68
6-31 Alternate Bus Master Mod e ...................... .......... ............. ....................... ........................ ......... 6-69
6-32 Variable L atency IO .............. ....................... .......... ............. ........................ .................... .........6-69
6-33 Asynchron ous Boot Time C onfiguratio ns and Regist e r Defaults................... .......... ............. ... 6-74
6-34 SMROM Boot T ime Configur ations and Re gister Defau lts.................. ....................... .............6 -75
6-35 SMROM Boot T ime Configur ations and Re gister Defau lts.................. ....................... .............6 -76
7-1 LCD Contro ller Block Dia gram ....... ....................... ....................... ........................ .......... ...........7- 3
7-2 Temporal Di thering Co ncept - Singl e Color..................... ....................... ........................ ........... 7-6
7-3 Compare Rang e for TMED ................ .......... ............. ........................ ....................... .......... ........7 -7
7-4 TMED Block Diagram ............. ... ........................ ....................... ....................... .... .................... . 7-8
7-5 Palette Buffe r Format .............. ... ........................ ....................... ... ........................ ...................7-11
7-6 1 Bit Per Pixel Data Memory Organiz ati o n ................... ... ....................... .... ....................... ...... 7-11
7-7 2 Bits Per P ixel Data Memory Organiza tion ................. ............. ....................... .......................7-12
7-8 4 Bits Per P ixel Data Memory Organiza tion ................. ............. ....................... .......................7-12
7-9 8 Bits Per P ixel Data Memory Organiza tion ................. ............. ....................... .......................7-12
7-10 16 Bits Per Pixel Data Memory Organization - Passive Mode ......... ............. ....................... ...7-13
7-11 16 Bits Per Pixel Data Memory Organization - Active Mo de ...................... ....................... ......7-13
7-12 Passive Mod e Start-of-Fra me Timing....................... ........................ ....................... ............. ... 7-15
7-13 Passive Mod e End-of-Frame Timing ..................... ....................... ........................ .......... .........7-15
7-14 Passive Mod e Pixel Cl ock and Data P in Timing........... ....................... ....................... ............. 7-16
7-15 Active Mod e Timing ................. ....................... ........................ .......... ............. .................... ......7-16
7-16 Active Mod e Pixel Cloc k and Data Pin Timing ....................... .......... ............. ....................... ... 7-17
7-17 Frame Buf fer/Palette O utput to L CD Data Pins i n Active Mod e .................... ....................... ...7-20
7-18 LCD Data- Pin Pixel Ordering............. .......... ............. ........................ ....................... ................7-22
8-1 Texas Instru ments’ Syn c hronous Seri al Fra me* For mat.................. ... ....................... ...............8-4
8-2 Motorola SP I* Frame Forma t ................ ........................ ....................... .......... ............. ...............8-5
8-3 National Micro wir e* Fra me For mat.............. ... ........................ ... ....................... ........................ .8-6
8-4 Motorola SP I* Frame Forma ts for SPO an d SPH Programmi ng ............ .......... .............. ......... 8-13
9-1 I
2
C Bus Config uration Example................ ....................... .......... ............. ........................ ........... 9-2
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9-2 Start and Stop Conditio ns............ ... ....................... ........................ ....................... ... ..................9-5
9-3 START and STOP Conditions .................. ............. ........................ ....................... .....................9-6
9-4 Data Format of First Byte in Master T ransaction ............. ........................ ....................... .......... .9-8
9-5 Acknowledge o n the I2C B us............. ........................ ....................... .......... ............. ..................9-9
9-6 Clock Synchro nization Dur ing the Arbit r ation Procedure........... .............. ....................... .........9-10
9-7 Arbitration Procedure of T wo Masters ................... .......... .............. ....................... .......... .........9-11
9-8 Master-Receiv e r Read from Slave-Transm itter ............... ........................ ....................... .........9-14
9-9 Mas t er- Receiver Re ad from Slave -Transmit t er / Repeated S tart / Master -T r ansmitter
Write to Slave-Rec eiv er ........ ... .... ....................... ....................... ........................ ... ...................9- 14
9-10 A Complete D a ta Transfer .............. ............. ........................ .......... ............. ....................... ...... 9-14
9-11 Master-Transmi tter Write to Slave-Receiv e r ........................ .......... ............. ....................... ...... 9-16
9-12 Master-Receiv e r Read to Slave-Transmit ter ...... ....................... .......... .............. ......................9-16
9-13 Mas ter-R eceiv er Read to Slave-Tran smitter, Re peated START, Mast er-Tran smitt er
Write to Slave-Rec eiv er ........ ... .... ....................... ....................... ........................ ... ...................9- 16
9-14 General Call Address..... .............. ....................... ....................... .......... .............. .................... .. 9-17
10-1 Example UAR T Data Frame ........ ............. ....................... ........................ ....................... .........10 -4
10-2 Example NR Z Bit Encodin g – (0b0100 1 011 ................... ........................ ....................... .........10-5
10-3 IR Transmit and Receive Example ........... ....................... ........................ ....................... .......10-25
10-4 XMODE Exampl e............... .......... ............. ....................... ........................ .......... ............. .......10-25
11-1 4PPM Modulatio n Encodings....... ....................... ....................... ........................ .......... ............11- 2
11-2 4PPM Modulatio n Example ................... ....................... .......... ............. ........................ ............1 1- 2
11-3 Frame Format f o r IrDA Transmission (4. 0 Mbps) ................ .......... ............. ....................... ......11-3
12-1 NRZI Bit E ncoding Exampl e .................. ....................... ....................... ........................ .......... .. 12-4
12-2 Self-Powere d Devi c e ................... ....................... ... ........................ ....................... .................12-11
13-1 Data Trans fer Through th e AC-link.............. .............. ....................... ....................... ................13-3
13-2 AC’97 Standard Bidi re ctio n al Aud io Frame .................. ... ........................ ... ....................... ...... 13-4
13-3 AC-link Au dio Output Fra m e..................... ....................... .......... .............. ....................... ......... 13 -5
13-4 Start of Aud io Output Fr ame ..................... ....................... .......... .............. ....................... .........13-5
13-5 AC’97 Input Frame......... .......... .............. ....................... ....................... .......... .............. ............13-9
13-6 Start of an Audio Inpu t Frame......... ............. ........................ ....................... ....................... ......13-9
13-7 AC-link Powerd ow n Timi ng...... ........................ ... ....................... ........................ ....................13-12
13-8 SDATA_IN Wa ke Up Signalin g.............. ....................... ....................... ........................ ..........13-13
13-9 PCM Transmit and Receive Operation ............ ....................... .......... ............. ........................13-27
13-10 Mic-in Rec eive-Only Ope ration.................... ........................ ....................... .......... ............. .... 13-29
13-11 Modem Transmi t and Recei ve Operation ..................... .......... ............. ........................ ..........13-32
14-1 I2S Data F ormats (16 bi ts)....... .......... .............. ....................... ....................... .......... ................ 14-7
14-2 MSB-Justifie d Data Formats (16 bits ..................... ........................ .......... ............. ...................14-7
14-3 Transmit a nd Receive FIF O Accesses Through the SA DR ................. ........................ ..........14-15
15-1 MMC System In teraction ................... ........................ ....................... ....................... .......... ......15-1
15-2 MMC Mode Operati on Without Da ta Token........ ....................... ........................ .......... ............15-3
15-3 MMC Mode Operati on With Da ta Token.......... .......... ............. ....................... ........................ ..15-3
15-4 SPI Mode Oper ation Withou t Data Token ................. ....................... .......... ............. ................15-4
15-5 SPI Mode Rea d Operation.... ....................... ........................ ....................... .......... ............. ..... .1 5-4
15-6 SPI Mode Writ e Operation ..................... .......... ............. ....................... ........................ .......... .. 15-4
16-1 Texas Ins truments Synchr onous Serial F rame* Protoc ol (multipl e transfers) ................... ...... 16-5
16-2 Texas Ins truments Synchr onous Serial F rame* Protoc ol (single transfers) ................... .........16-6
16-3 Motorola SPI* F rame Protocol (multiple transfers) .................... ........................ ......................16-7
16-4 Motorola SPI* F rame Protocol (single tr ansfers) .................... ............. ........................ ............16-7
16-5 Mot or ola SPI* Frame Pr otocols for SP O and SPH Program m ing (multip le
transfers).... .......... .............. ....................... ....................... ........................ .......... .......... ............16-8
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16-6 Moto ro la SPI* Frame P ro tocols for SP O a nd SPH Progr am m ing (single
transfers) .................... .......... ............. ....................... ........................ ....................... ....... .........16-9
16-7 National Semiconductor Microwire* Frame Protocol (multiple tr ansfers) ............. ............. .... 16-10
16-8 National Semiconductor Microwire* Frame Protocol (single tran sfers) ................ .......... .......16-10
16-9 Programmable Serial Protoc ol (multipl e transfers)................. ............. ....................... ........... 16-11
16-10 Programmable Serial Protocol (single tr ansfers).................... ............. ....................... ........... 16-12
16-11 TI SSP wit h SSCR[TTE]=1 and SSCR[ TTELP]=0.............. ........................ ....................... .... 16-13
16-12 TI SSP wit h SSCR[TTE]=1 and SSCR[ TTELP]=1.............. ........................ ....................... .... 16-14
16-13 Motorola SP I with SSCR[TTE]=1.......... .......... .............. ....................... ....................... ........... 16-14
16-14 National Se miconductor Microwire with SSCR1[TTE]= 1 ........... ....................... .....................16-15
16-15 PSP mode with SSCR1[TTE]=1 an d SSCR1[TTELP]= 0 (slave to fr ame) ............ ............. .... 16-15
16-16 PSP mode with SSCR1[TTE]=1 a nd SSCR1[TTELP]= 0 (master to frame) ............... ...........16-16
16-17 PSP mode with SSCR1[TTE]=1 an d SSCR1[TTELP]=1 (must be slav e to
frame) ............... ............. ....................... ........................ ....................... .......... ............. ...........16-16
17-1 Example U ART Data Fra me ........... ....................... ....................... ........................ .......... .........17-3
17-2 Example N RZ Bit Encodin g – (0b0100 1 011 ............ ........................ ....................... ................17-4
17-3 IR Trans mit and Recei v e Example ........... ....................... ....................... ........................ .........17-9
17-4 XMODE Example . ......... .......... ............. ........................ ....................... .......... ............. .............17-9
Tables
2-1 CPU Core Fa ult Regist er Bit Defin itions....................... ....................... ....................... .......... .....2-3
2-2 ID Bit Definiti o ns ............ ... ........................ ... ....................... ........................ .................... ........... 2-4
2-3 PXA255 Processor ID Value s......... ... ....................... ........................ ....................... ... ............... 2-4
2-4 Effect o f Each Type o f Reset on I nternal Registe r State .............. .............. ....................... ........ 2-6
2-5 Processor Pin Types ...................... ....................... ....................... .......... .............. .................... . 2-8
2-6 Pin & Sign al Descrip tions for the PX A255 Processor................... ........................ .....................2-9
2-7 Pin Desc ription Note s ................. .......... .............. ....................... ....................... .......................2-17
2-8 System Archit e cture Register Address S ummary ........ ............. ....................... .......................2-21
3-1 Core PLL O utput Frequen cies for 3.6 864 MHz Crys tal .................... ............. ....................... ..... 3-5
3-2 95.85 MHz Per ipheral PLL Output Fre quencies for 3 .6864 MHz Crys tal ................... .......... .....3-5
3-3 147.46 MHz Pe ripheral PL L Output Fr equencies f or 3.6864 MHz Crystal .............. ..................3-6
3-4 Power Mode En try Sequence Table ..................... ....................... ........................ .......... .........3-20
3-5 Power Mode Exit Sequence Table ................ ........................ ....................... .......... ............. ... 3-20
3-6 Power an d Clock Supp ly Sources a nd States Du ring Power Modes ........ ....................... ...... 3-22
3-7 PMCR Bit De finitions ............ ............. ....................... ........................ .......... ............. ................3-23
3-8 PCFR Bit Definitions................ ............. ........................ ....................... ....................... ....... ......3-24
3-9 PWER Bit De finitions.................. .......... .............. ....................... ....................... .................... ... 3-25
3-10 PRER Bit Definitions...... ............. ........................ ....................... ....................... .......... .......... ... 3-26
3-11 PFER Bit Definit ion s ............. ....................... ... ........................ ....................... .................... ......3-27
3-12 PEDR Bit Definitions...... ............. ........................ ....................... ....................... .......... .......... ... 3-28
3-13 PSSR Bit De finitions....................... ....................... ....................... .......... .............. ...................3-29
3-14 PSPR Bit De finitions....................... ....................... ....................... .......... .............. ...................3-30
3-15 PMFW Regist er Bitmap and Bi t Definitions ........... ....................... .......... .............. ...................3-31
3-16 PGSR0 Bit Definitions ................ .............. ....................... ....................... ........................ ...... ...3-32
3-17 PGSR1 Bit Definitions ................ .............. ....................... ....................... ........................ ...... ...3-32
3-18 PGSR2 Bit Definitions ................ .............. ....................... ....................... ........................ ...... ...3-33
3-19 RCSR Bi t Definition s ............ ....................... ....................... ........................ .............................3-34
3-20 CCCR Bit Defini tions ........ .... ....................... ....................... ........................ ............................. 3-35
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3-21 CKEN Bit Definition s............. ... ........................ ....................... ....................... .... .................... .. 3-36
3-22 OSCC Bit De finitions ............... .......... .............. ....................... ....................... .......... .......... ...... 3-38
3-23 Coprocessor 14 Clock and Power Manage ment Summary.............. ............. ........................ .. 3-39
3-24 CCLKCFG Bit Definitions... ....................... .......... ............. ........................ ....................... .........3-39
3-25 PWRMODE Bit Defini tio ns. ... ....................... ........................ ... ....................... ....................... ...3- 40
3-26 Clocks Manager Re gis ter Summary ......... ... ........................ ....................... ....................... .... .. 3-41
3-27 Power Manager Regis te r Summary... .... ... ....................... ........................ ....................... ... ...... 3-42
4-1 GPIO Alternate Functions............... ....................... ........................ .......... ............. .................... . 4-3
4-2 GPIO Regist er Definition s............... ....................... ........................ .......... ............. .................... .4-6
4-3 GPLR0 Bit De finitions ........... ....................... ........................ ....................... .............................. .4-7
4-4 GPLR1 Bit De finitions ........... ....................... ........................ ....................... .............................. .4-8
4-5 GPLR2 Bit De finitions ........... ....................... ........................ ....................... .............................. .4-8
4-6 GPDR0 Bit Definiti o ns ................. ....................... ... ........................ ....................... .................... . 4-9
4-7 GPDR1 Bit Definiti o ns ................. ....................... ... ........................ ....................... .................... . 4-9
4-8 GPDR2 Bit Definiti o ns ................. ....................... ... ........................ ....................... .................... . 4-9
4-9 GPSR0 Bit Definitions.... ........................ ....................... ... ........................ ....................... .........4-10
4-10 GPSR1 Bit Definiti ons.... .... ....................... ....................... .... ....................... .............................4-10
4-11 GPSR2 Bit Definiti ons.... .... ....................... ....................... .... ....................... .............................4-11
4-12 GPCR0 Bit Defini tio ns ............. .... ... ....................... ........................ ....................... ... ................4-11
4-13 GPCR1 Bit Defini tio ns ............. .... ... ....................... ........................ ....................... ... ................4-11
4-14 GPCR2 Bit Defini tio ns ............. .... ... ....................... ........................ ....................... ... ................4-12
4-15 GRER0 Bit Definiti o ns ................. ....................... ... ........................ ....................... ...................4-13
4-16 GRER1 Bit Definiti o ns ................. ....................... ... ........................ ....................... ...................4-13
4-17 GRER2 Bit Definiti o ns ................. ....................... ... ........................ ....................... ...................4-13
4-18 GFER0 Bit De finitions.............. ........................ ....................... ....................... .......... .......... ...... 4-14
4-19 GFER1 Bit De finitions.............. ........................ ....................... ....................... .......... .......... ...... 4-14
4-20 GFER2 Bit De finitions.............. ........................ ....................... ....................... .......... .......... ...... 4-14
4-21 GEDR0 Bit Defini tio ns ............. .... ... ....................... ........................ ....................... ... ................4-15
4-22 GEDR1 Bit Defini tio ns ............. .... ... ....................... ........................ ....................... ... ................4-15
4-23 GEDR2 Bit Defini tio ns ............. .... ... ....................... ........................ ....................... ... ................4-16
4-24 GAFR0_L Bit D e finitions ........................ ....................... .......... ............. ........................ ............4-17
4-25 GAFR0_U Bit Definition s ................ .......... ............. ........................ ....................... .......... .........4-17
4-26 GAFR1_L Bit D e finitions ........................ ....................... .......... ............. ........................ ............4-18
4-27 GAFR1_U Bit Definition s ................ .......... ............. ........................ ....................... .......... .........4-18
4-28 GAFR2_L Bit D e finitions ........................ ....................... .......... ............. ........................ ............4-19
4-29 GAFR2_U Bit Definition s ................ .......... ............. ........................ ....................... .......... .........4-19
4-30 ICMR Bit Definition s. ....................... ... ........................ ....................... ... ........................ ............4-22
4-31 ICLR Bit D efinitions..... ............. ........................ ....................... ....................... .......... .......... ...... 4-23
4-32 ICCR Bit Definition s .............. ............. ........................ ....................... ....................... ................4-23
4-33 ICIP Bit Definiti o ns............. ... ... ........................ ....................... ....................... .... .................... .. 4-24
4-34 ICFP Bit D efinitions..... ............. ........................ ....................... ....................... .......... .......... ...... 4-24
4-35 ICPR Bit De finitions .............. ............. ........................ .......... ............. ....................... ................4-25
4-36 List of Fi rst–Level I nterrupts .................. ....................... .......... ............. ........................ ............4-27
4-37 RTTR Bit De finitions .................... ....................... ....................... ........................ .......... .......... .. 4-30
4-38 RTAR Bit D efinitions ....................... .......... ............. ........................ ....................... ...................4-30
4-39 RCNR Bit De finitions ............... .............. ....................... ....................... ........................ ...... ......4-31
4-40 RTSR Bit D efinitions ....................... .......... ............. ........................ ....................... ...................4-32
4-41 OSMR[x] Bit Defini ti ons .................. ....................... ........................ ... ....................... ................4-36
4-42 OIER Bit De finitions..................... .......... ............. ....................... ........................ .................... ..4-36
4-43 OWER Bit Defi nitions..... .............. ....................... ....................... ........................ .................... .. 4-37
xviii Intel® PXA255 Processor Developer ’s Manual
Contents
4-44 OSCR Bit Definit i ons .................. .... ... ....................... ........................ ....................... ... .............4-37
4-45 OSSR Bit D e finitions ............ .......... ............. ....................... ........................ ..................... ........4-38
4-46 PWM_CTRLn Bit Definitions .......... .......... ............. ....................... ........................ .......... .........4 -4 1
4-47 PWM_DUTYn Bit Defi nit i ons ............. ....................... ........................ ... ....................... .............4 - 42
4-48 PWM_PERVALn Bit Definition s................... ....................... .......... .............. ....................... ...... 4-43
4-49 GPIO Registe r Addr ess es .................... .... ....................... ....................... .... ....................... ......4-44
4-50 Interrup t Controller Register Ad dresses ................ ....................... ........................ ...................4-45
4-51 RTC Registe r Addre ss es................ ... ....................... ........................ ....................... ................4-45
4-52 OS Timer R egister Addre sses ........... ....................... ........................ ....................... .......... ......4 -4 5
4-53 Pulse Wid th Modulator R egister Addre sses .................... ....................... ........................ ......... 4-46
5-1 DMAC Signal L ist ....... ....................... .......... ............. ........................ ....................... ..................5-2
5-2 Channel P riority (if all channels a re running concurrentl y) ..................... ........................ ........... 5-4
5-3 Channel P riority ................ .......... .............. ....................... ....................... .......... ............ .............5-4
5-4 Priority Sch emes Exa mple s........ ........................ ... ....................... ........................ .................... . 5-5
5-5 DMA Quick Reference for Inter n al Peri p hera ls .................. .... ....................... ... .......................5-13
5-6 DINT Bit De finitions .................... .............. ....................... ....................... .................................5 -17
5-7 DCSRx Bit Defin iti o ns.... ... .... ....................... ....................... ........................ ... .................... ...... 5-18
5-8 DRCMRx Bit Definitions .................... ....................... ........................ ....................... .......... ..... .5-20
5-9 DDADRx Bit Definition s ........... ....................... ........................ ....................... .......................... 5-21
5-10 DSADRx Bi t Definitio ns .................. ............. ....................... ........................ ............................. 5-22
5-11 DTADRx Bit Defi nit i ons .................. ... ....................... ........................ ... ....................... .............5-23
5-12 DCMDx Bit Definit ions .................... ....................... ....................... .... ....................... ................5-24
5-13 DMA Contr oller Regist er Summary ............. ............. ........................ ....................... .......... ......5-28
6-1 Device Tran sactions ............. ............. ....................... ........................ ....................... ..................6-7
6-2 MDCNFG Bit Defin i tio ns................. ... ....................... ........................ ....................... ... ...............6-9
6-3 MDMRS Bit Definitions ............ .......... ............. ........................ ....................... ..........................6-12
6-4 MDMRSLP Re gister Bit D efinitions ....................... ....................... ........................ ...................6-14
6-5 MDREFR Bit Definition s .................... ....................... ........................ ....................... .......... ..... .6-15
6-6 Sample SDRAM Me mory Size Opt ions .................... .......... .............. ....................... ................6-18
6-7 External t o Internal Address Mapping f or Normal Bank Addressing .................... .......... .........6-19
6-8 External t o Internal A ddress Mapping f o r SA-1111 Addressing ................. ....................... ...... 6-21
6-9 Pin Mapping to SDRAM Devi ces with N ormal Bank Ad dressing............ .......... .............. ......... 6-23
6-10 Pin Mappi ng to SDRAM De vices with S A1 111 Addressing................. ....................... .............6 -25
6-11 SDRAM Comma nd Encoding ............... ........................ .......... ............. ....................... .............6 -28
6-12 SDRAM Mode R egister Opc ode Table........... .............. ....................... .......... ............. .............6 -28
6-13 SXCNFG Bit Definit i ons........ ....................... ... ........................ ....................... ....................... ... 6-33
6-14 SXCNFG....... ........................ .......... ............. ....................... ........................ .......... .......... .........6-36
6-15 Synchronou s Static Memory External to Internal Address Mapping Optio ns ....................... ... 6-37
6-16 SXMRS Bit Defini tio ns................ .... ....................... ... ........................ ....................... ................6-38
6-17 Read Confi guration Reg ister Programmin g Values............ ........................ ....................... ......6-40
6-18 Frequenc y Code Co nf igu rati o n Values Bas ed on Clo ck Sp eed ............. ........................ ......... 6-40
6-20 16-Bit Bu s Write Acces s .................... ............. ........................ ....................... .......... .......... ...... 6-44
6-19 32-Bit Bu s Write Acces s .................... ............. ........................ ....................... .......... .......... ...... 6-44
6-21 MSC0/1/2 Bi t Definiti ons................. ....................... ....................... ........................ ...................6-45
6-22 Asynchronous Static Memory and Va riable Latency I/O Capabilities............ ....................... ...6 -48
6-23 MCMEM0/1 Bit Definitions....... .......... ............. ........................ .......... ............. ..........................6-58
6-24 MCATT0/1 Bit Defi n iti o ns ........... ........................ ... ....................... ........................ ...................6-59
6-25 MCIO0/1 Bi t Definitio n s ........... ....................... ........................ .......... ............. .................... ...... 6-59
6-26 Card Inter fa ce Comman d Asser ti o n Code Table.......... ....................... ....................... .............6 -60
6-27 MECR Bit Definition................. ............. ........................ ....................... ....................... .............6-61
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6-28 Common Memory Space Write Commands .................... ........................ ... ....................... .... .. 6-63
6-29 Common Memory Space Read Commands .......... .... ... ....................... ........................ ... .........6-63
6-30 Attribute Me mory Space Write Commands ..................... .............. ....................... ...................6-63
6-31 Attribute Me mory Space Rea d Commands ..................... .......... .............. ....................... .........6-63
6-32 16-Bit I/O S p ace Write Commands (nIOIS16 = 0) ........... ........................ .......... ............. .........6-63
6-33 16-Bit I/O S pace Read Commands (nIOIS1 6 = 0)............... ....................... ....................... ...... 6-63
6-34 8-Bit I/O Space Write Co mmands (nIOIS16 = 1) ....................... .......... .............. ......................6-64
6-35 8-Bit I/O Space Read Comman ds (nIOIS16 = 1)................. .......... ............. ....................... ...... 6-64
6-36 BOOT_SEL Defi nitions ............ .......... .............. ....................... .......... ............. ..........................6-72
6-37 BOOT_DEF Bitmap .............. ....................... ........................ .......... ............. ....................... ...... 6-73
6-38 Valid Boot Configurati ons Based on Pro cessor Type............. ............. ........................ .......... ..6-73
6-39 Memory Cont roller Pin Res et Values........ .......... ............. ........................ ....................... .........6-77
6-40 Memory Cont roller Regist er Summary ...................... ....................... .......... ............. ................6-79
7-1 Pin Descript ions.................... ....................... .......... .............. ....................... .................... .......... .7-4
7-2 LCD Controller Data Pin Utilizatio n.............. .............. ....................... .......... ............. ................7 -21
7-3 LCCR0 Bit Definitions ..................... .......... ............. ........................ ....................... ...................7-23
7-4 LCCR1 Bit Definitions ..................... .......... ............. ........................ ....................... ...................7-26
7-5 LCCR2 Bit Definitions ..................... .......... ............. ........................ ....................... ...................7-28
7-6 LCCR3 Bit Definitions ..................... .......... ............. ........................ ....................... ...................7-31
7-7 FDADRx Bit De finitions................ ............. ....................... ........................ ....................... .........7-33
7-8 FSADRx Bit De finitions ............ .......... .............. ....................... ....................... ..........................7-34
7-9 FIDRx Bit Definitions... ............. ........................ ....................... ....................... .................... ...... 7-34
7-10 LDCMDx Bit Defini ti o ns .................. ... ........................ ....................... ....................... .... ............7-36
7-11 FBRx Bit D efinitions........... ............. ....................... ........................ .......... ............. ...................7-37
7-12 LCSR Bit De finitions .................... ....................... .......... ............. ........................ .................... ..7-40
7-13 LIICR Bit Definit i ons. ....................... ....................... .... ....................... ....................... ................7-41
7-14 TRGBR Bit De finitions ................. ............. ....................... ........................ .......... ............. .........7-42
7-15 TCR Bit D efinitions .................. ........................ ....................... ....................... .......... ....... .........7-44
7-16 LCD Controlle r Regis te r Summary .................. ....................... ....................... .... ......................7-44
8-1 External In terface to Codec ............ ............. ........................ ....................... ....................... ........8-1
8-2 SSCR0 Bit De finitions.............. ........................ ....................... ....................... .................... ........8 -9
8-3 SSCR1 Bit De finitions.............. ........................ ....................... ....................... .................... ...... 8-11
8-4 TFT and RFT Values for DMA Serv icing ................... .......... ............. ....................... ................8-15
8-5 SSDR Bit Definiti ons............. ....................... .... ....................... ....................... .................... ......8-15
8-6 SSSR Bit D efinitions .......... ............. ....................... ........................ ....................... ...................8-17
8-7 SSP Controll er Registe r Summary ........... ............. ........................ ....................... .......... .........8-19
9-1 I2C Signal D escription .................... ....................... ........................ .......... ............. .................... . 9-1
9-2 I2C Bus Definitions .............. ... ........................ ....................... ... ........................ .................... .... 9-2
9-3 Modes of Operation .............. ... ........................ ... ....................... ........................ ... .................... . 9-3
9-4 START and STOP Bit Definiti ons ............. .......... ............. ........................ ....................... ...........9-4
9-5 Master Tran sactions ....................... ....................... ........................ .......... ............. ...................9-12
9-6 Slave Transa ctions ...................... ....................... ....................... .......... .............. .................... .. 9-15
9-7 General Call Ad dress Second Byte Defi nitions ...................... ....................... ........................ .. 9-17
9-8 IBMR Bit Definitions............. ... .... ....................... ....................... .... ....................... ...................9-22
9-9 IDBR Bit De finitions .................... ....................... ....................... ........................ .................... ..9-23
9-10 ICR Bit Definitions... ... ....................... ........................ ....................... ....................... ................9-23
9-11 ISR Bit Definitio ns............. ... ... ........................ ....................... ....................... .... .................... .. 9-26
9-12 ISAR Bit Definitions ................ ........................ ....................... ....................... .... .................... .. 9-27
10-1 UART Signal Descriptions ........... ............. ....................... ........................ ....................... ......... 10-3
10-2 UART Regist e r Addresses as Offset s of a Base .................... ....................... ........................ .. 10-6
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Contents
10-3 RBR Bit Definitions ........... .......... .............. ....................... ....................... .......... .......................1 0-6
10-4 THR Bit Defin iti o ns ........... ........................ ....................... ....................... .................................1 0-7
10-5 DLL Bit Definit ion s ............ ........................ ....................... ... ........................ .................... ......... 10-8
10-6 DLH Bi t Definitions .................. ....................... .......... .............. ....................... .................... ...... 10-8
10-7 IER Bit Definitions....... ............. ....................... .......... .............. ....................... .................... ......10-9
10-8 Interrup t Conditions .................... .............. ....................... ....................... ....................... ....... . 10-10
10-9 IIR Bit Definitions ........... .......... ............. ........................ ....................... .......... ........................10-10
10-10 Interrup t Identific ation Registe r Decode ............. ....................... ....................... .....................10-11
10-11 FCR Bit Defin iti o ns ..................... .... ....................... ....................... ........................ .................10-12
10-12 LCR Bit D efinitions ..................... ........................ ....................... ....................... .......... .......... . 10-14
10-13 LSR Bit De finitions......... ....................... .......... .............. ....................... ....................... ........... 10-15
10-14 MCR Bit Definitions .................... ........................ ....................... ....................... .................... . 10-18
10-15 MSR Bit Definit ion s........ ... ........................ ... ....................... ........................ .................... .......10-20
10-16 SPR Bit Definiti ons ..................... ........................ ....................... ....................... .... .................10-21
10-17 ISR Bit Definitions....... ............. ....................... .......... .............. ....................... .................... ....10-24
10-18 FFUART Regis te r Summary.... ... ........................ ... ....................... ........................ .................10-26
10-19 BTUART Reg ister Summary .................... ............. ....................... ........................ .......... .......10-26
10-20 STUART Reg ister Summary .................... ............. ....................... ........................ .......... .......10-27
10-21 Flow Control Regist e rs in BTUART and STUART........ ... ... ........................ ....................... .... 10-28
11-1 FICP Signal Desc rip tio n ................. ... ... ........................ ....................... ... ........................ ......... 1 1-1
11-2 ICCR0 Bit Definition s ............ ............. ....................... ........................ .......... ............. ................11-8
11-3 ICCR1 Bit Definition s ............ ............. ....................... ........................ .......... ............. ..............11-10
11-4 ICCR2 Bit Definition s ............ ............. ....................... ........................ .......... ............. ..............11-11
11-5 ICRD Bit Definit i ons................. ....................... .... ....................... ....................... .................... . 11-12
11-6 ICSR0 Bit Definitions ............ ....................... ....................... .......... .............. ........................... 11-13
11-7 ICSR1 Bit Definitions ............ ....................... ....................... .......... .............. ........................... 11-15
11-8 FICP Registe r Summary....... ... ....................... ........................ ... ....................... .....................11 -16
12-1 Endpoint Co nfig u rati o n ............ ... ........................ ....................... ....................... .... ...................12-2
12-2 USB States ............. .... ....................... ....................... .... ....................... ....................................12-3
12-3 IN, OUT, and SETUP Token Packet F orm at ............ .... ....................... ... ........................ ......... 12-5
12-4 SOF Token Packet Form at................ ... .... ....................... ....................... ........................ ... ...... 12-5
12-5 Data Packe t Format.................... .............. ....................... ....................... .......... .............. .........1 2-6
12-6 Handshak e Packe t Forma t ............. ....................... ....................... ........................ ... ................12-6
12-7 Bulk Tran saction Forma ts............... ............. ....................... ........................ .......... ............. ...... 12-7
12-8 Isochron ous Tra ns ac ti o n Formats ............ ....................... ....................... ........................ ... ...... 12-7
12-9 Control Transaction Formats ................ ........................ ....................... .......... ............. .............12-7
12-10 Interrup t Transaction Formats .............. ........................ ....................... .......... ............. .............12-8
12-11 Host Devi ce Request Su mmary ........ ....................... .......... .............. ....................... ................12-9
12-12 UDCCR Bit Definitions................ .............. ....................... ....................... ........................ ...... . 12-22
12-13 UDC Contr ol Function Re gister ................ ....................... ....................... .......... .............. .......12-24
12-14 UDCCS0 B it Definit ions ........... .......... ............. ........................ ....................... .......... .......... .... 12-25
12-15 UDCCS1/6 /11 Bit Defi nitions.................... .......... ............. ....................... ........................ ....... 12 -27
12-16 UDCCS2/7 /12 Bit Defi nitions.................... .......... ............. ....................... ........................ ....... 12 -29
12-17 UDCCS3/8 /13 Bit Defi nitions.................... .......... ............. ....................... ........................ ....... 12 -31
12-18 UDCCS4/9 /14 Bit Defi nitions.................... .......... ............. ....................... ........................ ....... 12 -33
12-19 UDCCS5/1 0/15 Bit Def initions..................... ....................... ........................ .......... ............. .... 12-34
12-20 UICR0 Bit Definitions ............... ....................... ........................ ....................... .................... ....12-37
12-21 UICR1 Bit Definitions ............... ....................... ........................ ....................... .................... ....12-38
12-22 USIR0 Bit Definitions ............ ....................... .......... ............. ........................ .................... ....... 12-39
12-23 USIR1 Bit Definitions ............ ....................... .......... ............. ........................ .................... ....... 12-41
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Contents
12-24 UFNHR Bit Definition s ................. ....................... ....................... .......... .............. ....................12-43
12-25 UFNLR Bit D efinitions.............. .............. ....................... ....................... ........................ ..........12-44
12-26 UBCR2/4/7/9 /12/14 Bit De finitions..... ........................ ....................... .......... ............. ..............12-45
12-27 UDDR0 Bit Definitions ....... ............. ....................... ........................ ....................... .................12-46
12-28 UDDR1/6/11 Bit Defini tions ...................... ....................... ........................ ....................... .......12-46
12-29 UDDR2/7/12 Bit Defini tions ...................... ....................... ........................ ....................... .......12-47
12-30 UDDR3/8/13 Bit Defini tions ...................... ....................... ........................ ....................... .......12-47
12-31 UDDR4/9/14 Bit Defini tions ...................... ....................... ........................ ....................... .......12-48
12-32 UDDR5/10/1 5 Bit Defin itions .................... ....................... .......... .............. ....................... .......12-48
12-33 USB Device Controller Register Summary...................... ........................ .......... ............. .......1 2-48
13-1 External In terface to CODECs.................. ............. ........................ ....................... ...................13-2
13-2 Supported D ata Stream For mats................. ........................ .......... ............. ....................... ...... 13-3
13-3 Slot 1 Bit Definition s. ... ....................... ........................ ... ....................... ....................................13-7
13-4 Slot 2 Bit Definition s. ... ....................... ........................ ... ....................... ....................................13-7
13-5 Input Slot 1 Bit Defini tions........ .......... .............. ....................... .......... ............. .................... ....13-10
13-6 Input Slot 2 Bit Defini tions........ .......... .............. ....................... .......... ............. .................... ....13-11
13-7 GCR Bit De finitions............... .......... ............. ........................ ....................... .......... .................13-20
13-8 GSR Bit Definiti o ns ........ .... ....................... ... ........................ ....................... .................... .......13-22
13-9 POCR Bit De finitions ............... .............. ....................... ....................... ........................ ..........13-23
13-10 PICR Bit De finitions ................. ........................ ....................... ....................... .......... .......... .... 13-24
13-11 POSR Bit De finitions...... ........................ ....................... ....................... ........................ ...... ....13-25
13-12 PISR Bit Definit ion s ........... ... ... ........................ ....................... ....................... .... ....................13-25
13-13 CAR Bit Definition s .................. ........................ ....................... ... ........................ ....................13-26
13-14 PCDR Bit De finitions...... ........................ ....................... ....................... .......... .............. ..........13-26
13-15 MCCR Bit Defini tio ns...................... ... ........................ ....................... ....................... ..............13-27
13-16 MCSR Bit D efinitions ................... .......... ............. ....................... ........................ ....................13-28
13-17 MCDR Bit Defini tio ns...................... ... ........................ ....................... ....................... ..............13-28
13-18 MOCR Bit De finitions............... ........................ .......... ............. ....................... .................... .... 13-29
13-19 MICR Bit Definit ion s. ... ....................... ........................ ....................... ....................... .... ..........13-30
13-20 MOSR Bit Definiti o ns ......... ... ....................... ........................ ....................... ... .................... .... 13-30
13-21 MISR Bit D efinitions........... .......... ............. ....................... ........................ ..............................1 3-31
13-22 MODR Bit De finitions............... ........................ .......... ............. ....................... .................... .... 13-31
13-23 Address Mapp ing for CODEC Registers ............... .......... .............. ....................... .................13-33
13-24 Register Ma pping Summary ..................... ....................... .......... .............. ....................... .......13-35
14-1 External In terface to CODEC.......... .......... ............. ........................ ....................... ...................14 -2
14-2 Supported Sa mpling Frequen cies .. ............. ........................ ....................... .......... ............. ...... 14-6
14-3 SACR0 Bit Definition s ........ ............. ....................... ........................ ....................... .......... .........14-9
14-4 FIFO Write/ Read table............. .............. ....................... ....................... ........................ ..........14-10
14-5 TFTH and RFTH Values for DM A Servicing ................. ....................... ........................ ..........14-10
14-6 SACR1 Bit Definition s ........ ............. ....................... ........................ ....................... .......... .......14-11
14-7 SASR0 Bit Definitions ........ ............. ....................... ........................ ....................... .................14-12
14-8 SADIV Bit Definiti ons...................... ....................... ........................ ... ....................... ..............14-13
14-9 SAICR Bit Definitions............ ............. ........................ ....................... ....................... ..............14-13
14-10 SAIMR Bit D escriptions ............... ............. ....................... ........................ .......... ............. .......14-14
14-11 SADR Bit Descript i ons............. .... ....................... ....................... ........................ ....................14-14
14-12 Register Me mory Map ....................... ........................ ....................... .......... ............. ..............14-16
15-1 Command Token Format................... ........................ .......... ............. ....................... ................15-2
15-2 MMC Data To ken Format ...................... ....................... ....................... .......... .............. ............15-2
15-3 SPI Data To ken Format ........... ........................ ....................... .......... ............. ..................... ..... 15-2
15-4 MMC Signal Des cription .................... .......... .............. ....................... .......... ............. ................15-6
15-5 MMC_STRPCL Bit Defi nit i ons.................. ... ....................... ........................ ....................... ... . 15-23
15-6 MMC_STAT Bit Definitions ............. ............. ....................... ........................ .......... ............. .... 15-23
15-7 MMC_CLK Bit Definitions ........... ........................ .......... ............. ....................... .....................15 -25
15-8 MMC_SPI Bit D e finitions ...................... ........................ ....................... .......... ............. ...........15-25
15-9 MMC_CMDAT Bit Defi n itio n s ................... ....................... ....................... ........................ ... .... 15-26
15-10 MMC_RESTO Bit Definitions.................... ....................... .......... ............. ........................ .......15-27
15-11 MMC_RDTO R egister ....................... ....................... .......... .............. ....................... .............. 15-2 8
15-12 MMC_BLKLEN Bi t Definitio n s ........... ....................... ........................ .......... ............. ..............15-29
15-13 MMC_NOB Bit Definition s .................... .......... .............. ....................... ....................... ........... 15-2 9
15-14 MMC_PRTBUF Bit Defini tions.............. .............. ....................... ....................... .....................15-30
15-15 MMC_I_MASK Bit Definitions ............ ............. ........................ ....................... ....................... .15 -30
15-16 MMC_I_REG Bit Definitions ................. ........................ .......... ............. ....................... ........... 15-32
15-17 MMC_CMD Registe r .................. .... ....................... ....................... .... ....................... ..............15-33
15-18 Command Index Values .................... ... ........................ ....................... ... ........................ ....... 15 -33
15-19 MMC_ARGH Bit Def init i ons........ ........................ ....................... ....................... .... .................15-35
15-20 MMC_ARGL Bit Defi n iti o ns ............ ....................... ....................... .... ....................... ..............15-35
15-21 MMC_RES, FIF O Entry .................. ....................... .......... ............. ........................ ................. 15-36
15-22 MMC_RXFIFO, FIF O Entry ...................... ... ....................... ........................ ... ....................... . 15-36
15-23 MMC_TXFIFO, FIFO Entry......... .............. ....................... .......... ............. ........................ .......15-37
15-24 MMC Controll er Registers .................... ........................ .......... ............. ....................... ...........15-37
16-1 SSP Serial Port I/O Signals ............ ... ....................... .... ....................... ....................... .... .........1 6-2
16-2 Programmable Serial Protoc ol (PSP) Para meters ....... ............. ....................... .....................16-12
16-3 SSCR0 Bit Defini ti ons.... ....................... ........................ ....................... ... ........................ ....... 16-19
16-4 SSCR1 Bit Defini ti ons.... ....................... ........................ ....................... ... ........................ ....... 16-21
16-5 SSPSP Bit Definition s.... ... ........................ ... ....................... ........................ ........................... 16-23
16-6 SSTO Bit Definitions................ ............. ........................ ....................... .......... ............. ...........16-24
16-7 SSITR Bit Definitions ............ .......... ............. ....................... ........................ .................... .......16-25
16-8 SSSR Bit De finitions....................... ....................... ....................... .......... .............. .................16-26
16-9 SSDR Bit Definitions...... ............. ........................ ....................... ....................... .......... .......... . 16-29
16-10 NSSP Regi ster Address Ma p ............ .......... ............. ........................ ....................... .......... ....16-29
17-1 UART Sig nal Descript ions .................... .......... .............. ....................... ....................... .......... ... 17-3
17-2 RBR Bit Definitions ........... .......... .............. ....................... ....................... .......... ..................... 17-10
17-3 THR Bit Defin iti o ns ........... ........................ ....................... ....................... ............................... 17-10
17-4 DLL Bit Definit ion s ............ ........................ ....................... ... ........................ .................... ....... 17-11
17-5 Diviso r Latch Regi ster High ( DLH) Bit De finitions .... ........................ ....................... ..............17-11
17-6 IER Bit Definitions....... ............. ....................... .......... .............. ....................... .................... ....17-12
17-7 Interrup t Conditions .................... .............. ....................... ....................... ....................... ....... . 17-13
17-8 IIR Bit Definitions ........... .......... ............. ........................ ....................... .......... ........................17-13
17-9 Interrup t Identific ation Registe r Decode ............. ....................... ....................... .....................17-14
17-10 FCR Bit Defin iti o ns ..................... .... ....................... ....................... ........................ .................17-15
17-11 FOR Bit De finitions ............... ....................... ....................... ........................ .......... .......... ....... 17-16
17-12 ABR Bit Definiti ons ..................... ........................ ....................... ....................... .... .................17-17
17-13 ACR Bit Definitions ........... .......... .............. ....................... ....................... .............................. . 17-18
17-14 LCR Bit D efinitions ..................... ........................ ....................... ....................... .......... .......... . 17-18
17-15 LSR Bit De finitions......... ....................... .......... .............. ....................... ....................... ........... 17-20
17-16 MCR Bit Definitions .................... ........................ ....................... ....................... .................... . 17-22
17-17 MSR Bit Definit ion s........ ... ........................ ... ....................... ........................ .................... .......17-23
17-18 SCR Bit Definitions ........... .......... .............. ....................... ....................... .............................. . 17-24
17-19 ISR Bit Definitions....... ............. ....................... .......... .............. ....................... .................... ....17-25
17-20 HWUART Registe r Loca ti o ns ............ ... ........................ ....................... ... ........................ ....... 17-25
Intel® PX A255 Processor De veloper’s Man ual xxiii
Contents
xxiv Intel® PXA255 Processor Developer’s Manual
Contents
Revision History
Date Revision Description
March 2003 -001 Initial release
Intel® PX A255 Processor De veloper’s Man ual 1-1
Introduction 1 This document applies to the Int el® PXA255 Processor (PXA255 pro ces s or). It is an application
spec ific stand ard product (ASSP) that provides i ndu stry-leading MI PS/mW performan ce for
handheld computing appli catio ns. The processor is a highly inte grated system on a chip and
includes a h igh-performance lo w-power Intel® X S cale™ microarchitecture with a variety of
different system pe ripheral s.
The PXA255 proc esso r is a 17x17mm 256-pin PBG A package config uration fo r high per forma nce.
The 17x17m m pa ckage has a 32-bit memory da ta bu s and the ful l assortment of peripher als.
1.1 Intel® XScale™ Microarchitecture Feat ures The Intel® XScal e™ microarchitectur e provides these f eatures:
• ARM* Architecture V ersion 5TE ISA compliant.
— ARM* Thumb Ins truction S upp ort
— ARM* DSP Enhance d Instruct ions
• Low power cons um ption and hi gh performance
• Intel® Media Pro cessing T echnology
— Enhanced 16-b it Multiply
— 40-bit Accumulato r
• 32-KByte Instruction Cache
• 32-KByte Data Cache
• 2-KByte M ini Data Cache
• 2-KByte Mini Instr uction Cache
• Instructio n and Data Memor y Ma na gement Units
• Branch T ar get Buffer
• Debug Capabil ity via JT AG Port
Refer to the Int e l® XScale™ Micr oar chitecture for the I n tel® PXA255 Pr ocessor User’ s Manual
for more detai l s.
1.2 System Integration Features The processor integrat es the In tel® XScale™ microarchitectur e wit h this peripheral set:
• Memory C ontroller
• Clock and Power Con trollers
• Universal Serial Bus Client
1-2 Intel® PXA2 55 Process o r Developer’s Manual
Introduction
• DMA Controller
• LCD Controller
• AC97
• I
2
S
• MultiMediaCard
• FIR Communication
• Synchronous Serial Pro t oc o l Port
• I
2
C
• General Purp os e I/O pins
• UAR T s
• Real-Time Clock
• OS Timer s
• Pulse Width Modulation
• Interru p t C on t ro l
1.2.1 Memory Controlle r The Memory Con tro ller provides glueless control s i gn als with programmable tim in g for a wide
assortment of mem or y -chip typ es and organi zations. It supports up to four S DRA M partitions; six
static chip s elects for SRA M, S SRAM, F lash , ROM , SROM, and compa nion chip s; su pport for two
PCMCIA o r C ompa c t Flas h s lots
1.2.2 Clocks a nd Power Contr oller s The processor functional blocks are dr iv en by clocks that are deri ve d f rom a 3.6864-MHz crystal
and an o ptional 32. 768-kHz crystal.
The 3.6864-MHz crystal drives a core Phase Lock ed Loo p ( PLL) and a Per iph eral PLL. The PLLs
produce selec t e d clock frequencies to run particular functional bl ocks.
The 32.768-kH z crystal pr ovides an optional clock sour ce that must be selected aft er a hard rese t.
This clock drive s the Real T ime Clock (R TC), Power Manag ement Controll er, and Interrupt
Controller . The 32.768-kHz crystal is on a separate power island to provide an active clock while
the processor is in s lee p m ode.
Power managem ent control s the transiti on between the tu rbo/run, idle, and sleep operating m ode s .
1.2.3 Unive r sal Se rial Bus (USB ) Clien t The USB Client Module is bas ed on the Universal Serial Bus Specific ation, Revisio n 1. 1. It
supports up to s ix teen endpoints and it prov ides an interna l ly generated 48-MHz clo ck. The USB
Device Controller provides FIF Os with DMA access to or from memory .
Intel® PX A255 Processor De veloper’s Man ual 1-3
Introduction
1.2.4 DMA Controller (DMAC) The DMAC provide s six teen prioritized channels to service tran sfer requests from inte rnal
peripherals and up to two dat a tra nsfer requests from extern al companion chips. The DMAC is
descripto r-based to allow comma nd c h aining and looping const ructs.
The DMAC op e ra t e s in Fl ow -Throu gh Mo de wh e n pe rf or ming peri p he r a l- to -m emory, memory- to -
peripheral, and memory- to- m emory transfers. The DMAC is compatibl e with per ipherals that use
word, h alf-word, or byte data si zes.
1.2.5 LCD Controller The LCD Controller supports both passi ve (DSTN ) and active (TFT) flat-panel displ ays with a
maximum sup ported resol ution of 640 x48 0x16-bit/pixel. An inter nal 256 entry palette expa nd s 1,
2, 4, or 8-bit enc oded pixels. Non-encoded 16-bit pixel s bypass the pa lette.
T wo dedicated DMA channels a l l ow the LCD Controller to sup port single- and dual-pane l
displays . P a s sive monochr ome mode supp or ts up to 256 gra y- scale levels and passive col or mode
supports up to 64K colors . Active colo r mode suppo rts up to 64K colo rs.
1.2.6 AC97 Control ler The AC97 Control ler supports AC97 Revision 2.0 C ODECs. These CODECs can operate at
sample rates up to 48 KHz. The controller provi d es independent 16-bit chann els for S tereo PCM
In, Stereo PCM Out, Modem In , Mod em Out, and mono Microphone In. Each channel includes a
FIFO that su pports DMA access to memory.
1.2.7 Inter-IC Sound (I
2
S) Controller
The I
2
S Contro ller provides a s erial l ink to standard I
2
S CODECs for d igital ster eo sound. It
supports both th e Normal-I
2
S and MSB-Justif ied I
2
S forma ts, and provides four sig nals for
connectio n to a n I
2
S CODEC. I
2
S Controller signals are multiplexed with AC97 Controller pins.
The controller includes FIFOs that support DMA access to memory .
1.2.8 Multimedia Card (MMC) Controller The MMC Controller provide s a serial i nterface to sta ndard me mory cards . The controller suppor ts
up to two cards in e it her MMC or SPI modes with serial da ta tr ansfers up to 20 Mbps. Th e MMC
controller has FIFOs that s upport DMA access to and from memory .
1.2.9 Fast Infrared (FIR) Communication Port The FIR Co m munication Port is based on the 4-Mbps I nfrared D ata Assoc iation (IrDA)
Specification. It oper ates at half-duplex and has FIFOs with DMA access to memory . The FIR
Communication Port uses the S TUAR T ’ s transmit and receiv e pins to directly connect to ex ternal
IrDA LED transceivers.
1-4 Intel® PXA2 55 Process o r Developer’s Manual
Introduction
1.2.10 Synchronous Serial Protocol Controller (SSPC) The SSP Port provides a full-duplex synchr onous serial interface th at ope rates at bit rates from
7.2 kHz to 1. 84 MHz. It supports Nati onal Semico ndu ctor ’ s Microwir e*, T exas Instruments’
Synchronous Serial Protocol * , and Motorola’ s Serial Peripheral Interface*. The SSPC has FI FO s
with DMA a ccess to memory .
1.2.1 1 Inter-Integrated Circuit (I
2
C) Bus Inter face Unit
The I
2
C Bus Interface Unit provides a genera l purpose 2-pin serial communi cation port.The
interface uses one pin for data and address and a second pin for clock ing.
1.2.12 GPIO Each GPIO pin can be individua lly programmed as an outpu t or an input. Inputs can cau s e
interrupts on rising or f alling edge s . Primary GPI O pins are not shared with per ipherals while
secondary GPIO p ins have alter nate functions which can b e mapped to t he peripherals.
1.2.13 UART s The processor provides three Univers al Asyn chronous Receiver/T ransmitters. Each UART can be
used as a slow infrared (SIR) transmitt er /receiver based on the Infrared Data Associatio n Serial
Infrar e d (SIR) Ph ysical La yer Link Specifica tion.
1.2.13.1 Full Function UART (FFUART) The FFUAR T baud rate is pr og ramm abl e up to 2 30 Kbps. The FFUAR T provides a c omp lete se t of
modem control pins: nCTS, nR TS, nDSR, nDTR, nRI, and nDCD. It has FIFOs with DMA access
to or from memor y .
1.2.13.2 Bluetooth UART (BTUART) The BTUAR T baud rate is programma ble up to 921 Kbps. The BTUAR T provide s a partial set of
modem contro l pins: nCTS an d nR TS. Other mod em control pi ns can be implem ented via GPI Os.
The BTUART has FIFOs wi th DMA access to or from memory .
1.2.13.3 Standard UAR T (STUART) The STUA RT baud rate is pr og r ammab le up to 23 0 Kbps. The S TU ART does not prov i de any
modem contro l pins. The mode m control pin s can be impleme n ted via GPIOs. The STUAR T has
FIFOs wit h DM A a c ces s to or from memory.
The STUART’ s transmit and receive pins are multipl exed with the Fast Infrared Communicat ion
Port.
Intel® PX A255 Processor De veloper’s Man ual 1-5
Introduction
1.2.13.4 Hardware UART (HWUART) The PXA255 p rocessor has a U AR T with hardware flow co ntrol. The HWUAR T provides a partial
set of modem contr ol pins: nCTS and nR TS. These modem control pi ns pr ovi de full hardwar e f low
control. Ot her modem control pins can be implemented via GPIOs. The HWUAR T baud rate is
program mable u p to 92 1.6 Kbps.
The HWUAR T’ s pi ns are multiple xed with the PCMCIA contr ol pins. Because of thi s, these
HWUAR T pins operate at the same vo ltage as the memory bus. Also, since the PCMCIA pin
nPWE is used for variab le-latency input/output (VLIO), whil e using these pins for the H WUAR T ,
VLIO is unavailabl e. The HWUART pin s are also available ov er the BTUAR T pins. When
operating over th e BTUART pi ns, the HWUART pins operate at the I/O voltage.
1.2.14 Real-Ti me Clock (RTC) The Real-Time Clo ck can be clocked from either crys tal . A system with a 32.768-KHz cry st al
consumes le ss p owe r d ur ing Sl eep v ers u s a s ystem usi ng o nly th e 3.68 64- MHz crys tal. Th is cr ysta l
can be remov e d to save syst e m co s t. The R TC provides a consta nt f r equenc y ou tput with a
programmable alarm regis ter . This alarm register can be used t o w ake up the processor from Sleep
mode.
1.2.15 O S Timer s The OS T imers can be used to prov ide a 3. 68-MHz reference cou nter with f our match registers.
These registers can be config ure d to cause interrupts when equal to th e ref er ence counter . One
match register can be used to cause a watch do g reset.
1.2.16 Puls e-Wi dth Modul ator (PWM) The PWM has two in dependent outputs that can be progra m m ed to drive tw o GPIOs. The
frequency and duty cycle are ind epen dently programmable. For example, one GPIO can control
LCD contras t and the other LCD brigh t ne s s.
1.2.17 Interrupt Control The Interrupt Cont r oller directs the processor inter rupts into the cor e’s IRQ and FIQ inputs . The
Mask Registe r enables or dis a bl es individ ual interrupt sources.
1.2.18 Network Synchronou s Serial Protocol Port The PXA2 5 5 pr oc e s so r ha s a n SSP port optim iz e d f or con n e c ti o n to ot he r ne t w ork ASICs . T hi s
NSSP adds a Hi-Z functio n to TX D, the ability to control when Hi-Z occur s , and swapping the
TXD/RXD pi ns.
This port is not mult iplexed with other interfaces.
1-6 Intel® PXA2 55 Process o r Developer’s Manual
Introduction