Intel® CoreTM 2 Duo Processor and
Intel ® Q35 Express Chipset
Development Kit
User’s Manual
October 2007
Order Number: 318476-001US
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details.
The Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/ products/ht/Hyperthreading_more.htm for additional information.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
BunnyPeople, Celeron, Celeron Inside, Centrino, Centrino logo, Core Inside, FlashFile, i960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Core, Intel Inside, Intel Inside logo, Intel. Leap ahead., Intel. Leap ahead. logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel Viiv, Intel vPro, Intel XScale, IPLink, Itanium, Itanium Inside, MCS, MMX, Oplus, OverDrive, PDCharm, Pentium, Pentium Inside, skoool, Sound Mark, The Journey Inside, VTune, Xeon, and Xeon Inside are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others. Copyright © 2007, Intel Corporation. All Rights Reserved.
Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit |
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User’s Manual |
October 2007 |
2 |
Order Number: 318476-001US |
Contents—Intel Core 2 Duo Processor and Intel Q35 Express Chipset
1.0 About This Manual ..................................................................................................... |
6 |
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1.1 |
Content Overview................................................................................................ |
6 |
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1.2 |
Text Conventions ................................................................................................ |
6 |
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1.3 |
Glossary of Terms and Acronyms........................................................................... |
7 |
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1.4 |
Support Options.................................................................................................. |
8 |
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1.4.1 |
Electronic Support Systems ....................................................................... |
8 |
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1.4.2 |
Additional Technical Support ...................................................................... |
8 |
1.5 |
Product Literature ............................................................................................... |
8 |
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2.0 Development Kit Hardware Features ....................................................................... |
10 |
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2.1 |
Intel® Q35 Express Chipset Development Kit Overview.......................................... |
10 |
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2.2 |
System Block Diagram ....................................................................................... |
11 |
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2.3 |
Development Kit Inventory Checklists .................................................................. |
12 |
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2.4 |
Processor Support ............................................................................................. |
14 |
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2.5 |
System Memory ................................................................................................ |
14 |
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2.5.1 Dual Channel (Interleaved) Mode Configurations ........................................ |
15 |
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2.5.2 Single Channel (Asymmetric) Mode Configurations...................................... |
17 |
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2.6 |
Back-Panel Connectors....................................................................................... |
18 |
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2.6.1 |
Audio-Connectors................................................................................... |
18 |
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2.6.2 RJ-45 LAN Connector with Integrated LEDs................................................ |
19 |
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2.6.3 |
USB Port ............................................................................................... |
19 |
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2.6.4 Coaxial S/PDIF In/Out Connector.............................................................. |
19 |
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2.6.5 |
eSATA Port ............................................................................................ |
19 |
2.7 |
Debug Features................................................................................................. |
20 |
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2.7.1 |
Extended Debug Probe (XDP)................................................................... |
20 |
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2.7.2 |
Power LEDs ........................................................................................... |
20 |
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2.7.3 Port 80 POST Code LEDs ......................................................................... |
20 |
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2.7.4 |
Voltage Reference .................................................................................. |
21 |
2.8 |
Development Kit Major Connectors and Jumpers.................................................... |
21 |
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2.8.1 |
Jumper Functions ................................................................................... |
22 |
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2.8.2 USB 2.0 Front Panel ............................................................................... |
22 |
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2.8.3 |
1394a Header ........................................................................................ |
22 |
2.9 |
SPI Removal / Installation Technique ................................................................... |
23 |
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2.9.1 |
SPI Device Removal................................................................................ |
24 |
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2.9.2 |
SPI Device Installation ............................................................................ |
24 |
3.0 Setting Up and Configuring the Development Kit ..................................................... |
26 |
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3.1 |
Overview ......................................................................................................... |
26 |
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3.2 |
Installing Board Standoffs .................................................................................. |
26 |
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3.3 |
BTX Heatsink Setup with SRM ............................................................................. |
28 |
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3.3.1 SRM Alignment on any BTX Board ............................................................ |
28 |
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3.4 |
Board Setup and Configuration before Boot........................................................... |
30 |
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3.5 |
Post Codes Definitions........................................................................................ |
32 |
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3.5.1 |
Normal Post Codes ................................................................................. |
32 |
1 |
Board Features ........................................................................................................ |
11 |
2 |
Intel® Q35 Express Chipset Development Kit block diagram .......................................... |
12 |
3 |
Memory Channel and DIMM Configuration ................................................................... |
15 |
4 |
Dual Channel (Interleaved) Mode Configuration with 2x DIMMs ...................................... |
16 |
5 |
Dual Channel (Interleaved) Mode Configuration with 3x DIMMs ...................................... |
16 |
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Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit |
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October 2007 |
User’s Manual |
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Order Number: 318476-001US |
3 |
Intel Core 2 Duo Processor and Intel Q35 Express Chipset—Contents
6 |
Dual Channel (Interleaved) Mode Configuration with 4x DIMMs....................................... |
17 |
7 |
Single Channel (Asymmetric) Mode Configuration with 1x DIMM ..................................... |
17 |
8 |
Single Channel (Asymmetric) Mode Configuration with 3x DIMMs.................................... |
18 |
9 |
Back-panel Connectors.............................................................................................. |
18 |
10 |
LAN Connector LED locations...................................................................................... |
19 |
11 |
ITP-XDP Connector location (J2BC) ............................................................................. |
20 |
12 |
Major Jumper and Header Locations............................................................................ |
21 |
13 |
Location for 1394a Header and USB Front Panel ........................................................... |
23 |
14 |
SPI Socket with Retaining Clip.................................................................................... |
24 |
15 |
SPI Device Installation .............................................................................................. |
25 |
16 |
Intel® Q35 Development Kits .................................................................................... |
26 |
17 |
Mounting Hole Locations............................................................................................ |
27 |
18 |
Mounting the Standoff for BTX Heatsink....................................................................... |
28 |
19 |
Casing with “Support and Retention Module” ................................................................ |
28 |
20 |
BTX board alignment on SRM ..................................................................................... |
29 |
21 |
Heatsink Alignment................................................................................................... |
29 |
22 |
Tightening Heatsink on the SRM and Board .................................................................. |
30 |
23 |
CPU Fan location ...................................................................................................... |
31 |
24 |
2x12 Standard power supply and 2x2 power supply ...................................................... |
32 |
Tables |
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1 |
Definition ................................................................................................................. |
7 |
2 |
Intel Literature Centers .............................................................................................. |
9 |
3 |
Development Kit Hardware Items ............................................................................... |
12 |
4 |
Development Kit Board Specification ........................................................................... |
13 |
5 |
Internal I/O headers ................................................................................................. |
13 |
6 |
Supported Intel Technologies ..................................................................................... |
13 |
7 |
Additional Features ................................................................................................... |
14 |
8 |
LAN Connector LED status ......................................................................................... |
19 |
9 |
Voltage Reference detail............................................................................................ |
21 |
10 |
Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit Board |
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Jumpers Description ................................................................................................. |
22 |
11 |
USB Front Panel ....................................................................................................... |
22 |
12 |
1394a Header .......................................................................................................... |
23 |
Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit |
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User’s Manual |
October 2007 |
4 |
Order Number: 318476-001US |
Revision History—Intel Core 2 Duo Processor and Intel Q35 Express Chipset
Date |
Revision |
Description |
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October 2007 |
001 |
Initial release |
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Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit |
October 2007 |
User’s Manual |
Order Number: 318476-001US |
5 |
Intel Core 2 Duo Processor and Intel Q35 Express Chipset—About This Manual
This user’s manual describes the use of the Intel® Q35 Express Chipset Development Kit. This manual has been written for OEMs, system evaluators, and embedded system developers. All jumpers, headers, LED functions, and their locations on the board, along with subsystem features and POST codes, are defined in this document.
For the latest information about the Intel® Q35 Express Chipset Development Kit reference platform, visit:
http://developer.intel.com/design/intarch/devkits/ index.htm?iid=embed_body+devkits
For design documents related to this platform, such as schematics and layout, please contact your Intel Representative.
Chapter 1.0, “About This Manual”
This chapter contains a description of conventions used in this manual. The last few sections explain how to obtain literature and contact customer support.
Chapter 2.0, “Development Kit Hardware Features”
This chapter provides information on the development kit features and the board capability. This includes the information on board component features, jumper settings, pin-out information for connectors and overall development kit board capability.
Chapter 3.0, “Setting Up and Configuring the Development Kit”
This chapter provides instructions on how to configure the evaluation board and processor assembly by setting BTX heatsink, jumpers, connecting peripherals, providing power, and configuring the BIOS.
The following notations may be used throughout this manual.
# |
The pound symbol (#) appended to a signal name indicates that |
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the signal is active low. |
Variables |
Variables are shown in italics. Variables must be replaced with |
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correct values. |
Instructions |
Instruction mnemonics are shown in uppercase. When you are |
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programming, instructions are not case-sensitive. You may use |
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either upper-case or lower-case. |
Numbers |
Hexadecimal numbers are represented by a string of |
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hexadecimal digits followed by the character H. A zero prefix is |
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added to numbers that begin with A through F. (For example, FF |
Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit |
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User’s Manual |
October 2007 |
6 |
Order Number: 318476001US |
About This Manual—Intel Core 2 Duo Processor and Intel Q35 Express Chipset
is shown as 0FFH.) Decimal and binary numbers are represented by their customary notations (That is, 255 is a decimal number and 1111 1111 is a binary number). In some cases, the letter B is added for clarity.
Units of Measure |
The following abbreviations are used to represent units of |
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measure: |
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GByte |
gigabytes |
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KByte |
kilobytes |
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MByte |
megabytes |
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MHz |
megahertz |
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W |
watts |
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V |
volts |
Signal Names |
Signal names are shown in uppercase. When several signals |
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share a common name, an individual signal is represented by |
the signal name followed by a number, while the group is represented by the signal name followed by a variable (n). For example, the lower chip-select signals are named CS0#, CS1#, CS2#, and so on; they are collectively called CSn#. A pound symbol (#) appended to a signal name identifies an active-low signal. Port pins are represented by the port abbreviation, a period, and the pin number (e.g., P1.0).
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This section defines conventions and terminology used throughout this document. |
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Table 1. |
Definition |
(Sheet 1 of 2) |
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Term |
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Description |
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Advanced Digital Display Card – 2nd Generation. This card provides digital display options |
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for an Intel Graphics Controller that supports ADD2+ cards. It plugs into a x16 PCI |
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ADD2 Card |
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Express* connector but uses the multiplexed SDVO interface. The card adds Video In |
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capabilities to platform. This Advanced Digital Display Card will not work with an Intel |
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Graphics Controller that supports DVO and ADD cards. It will function as an ADD2 card in |
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an ADD2 supported system, but video in capabilities will not work. |
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ACPI |
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Advanced Configuration and Power Interface |
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Core |
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The internal base logic in the (G)MCH |
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DDR2 |
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A second generation Double Data Rate SDRAM memory technology |
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DMI |
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(G)MCH-IntelÆ ICH9 Direct Media Interface |
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DVI |
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Digital Video Interface. Specification that defines the connector and interface for digital |
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displays. |
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FSB |
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Front Side Bus. FSB is synonymous with Host or processor bus |
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GMA 3100 |
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Intel® Graphic Media Accelerator 3100 |
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Eighth generation I/O Controller Hub component that contains additional functionality |
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IntelÆ ICH9 |
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compared to previous ICHs. The I/O Controller Hub component contains the primary PCI |
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interface, LPC interface, USB2, ATA-100, and other I/O functions. It communicates with |
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the (G)MCH over a proprietary interconnect called DMI. |
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IGD |
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Internal Graphics Device. |
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LVDS |
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Low Voltage Differential Signaling. A high speed, low power data transmission standard |
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used for display connections to LCD panels. |
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Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit |
October 2007 |
User’s Manual |
Order Number: 318476001US |
7 |
Intel Core 2 Duo Processor and Intel Q35 Express Chipset—About This Manual
Table 1. |
Definition |
(Sheet 2 of 2) |
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Term |
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Description |
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Advanced Digital Display Card – 2nd Generation. This card provides digital display options |
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for an Intel Graphics Controller that supports ADD2+ cards. It plugs into a x16 PCI |
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ADD2 Card |
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Express* connector but uses the multiplexed SDVO interface. The card adds Video In |
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capabilities to platform. This Advanced Digital Display Card will not work with an Intel |
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Graphics Controller that supports DVO and ADD cards. It will function as an ADD2 card in |
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an ADD2 supported system, but video in capabilities will not work. |
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Memory Controller Hub component that contains the processor interface, DRAM |
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MCH |
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controller, and x16 PCI Express* port (typically, the external graphics interface). It |
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communicates with the I/O controller hub (Intel ICH9) and other I/O controller hubs over |
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the DMI interconnect. In this document MCH refers to the Intel® Q35 MCH component. |
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MEC |
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Media Expansion Card, also known as ADD2+ card. Refer to ADD2+ term for description. |
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Third Generation input/output graphics attach called PCI Express* Graphics. PCI Express* |
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PCI Express* |
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is a high-speed serial interface whose configuration is software compatible with the |
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existing PCI specifications. The specific PCI Express* implementation intended for |
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connecting the (G)MCH to an external Graphics Controller is a x16 link and replaces AGP. |
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The Primary PCI is the physical PCI bus that is driven directly by the ICH9 component. |
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Primary PCI |
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Communication between Primary PCI and the (G)MCH occurs over DMI. Note that the |
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Primary PCI bus is not PCI Bus 0 from a configuration standpoint. |
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Serial Digital Video Out (SDVO). SDVO is a digital display channel that serially transmits |
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digital display data to an external SDVO device. The SDVO device accepts this serialized |
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SDVO |
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format and then translates the data into the appropriate display format (i.e., TMDS, |
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LVDS, TV-Out). This interface is not electrically compatible with the previous digital |
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display channel - DVO. For the 82Q965 GMCH, it will be multiplexed on a portion of the |
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x16 graphics PCI Express* interface. |
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SDVO Device |
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Third party codec that uses SDVO as an input. May have a variety of output formats, |
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including DVI, LVDS, HDMI, TV-out, etc. |
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System Management Interrupt. SMI is used to indicate any of several system conditions |
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SMI |
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(such as, thermal sensor events, throttling activated, access to System Management |
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RAM, chassis open, or other system state related activity). |
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A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four x16 SDRAM |
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Rank |
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devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a |
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single side of a DIMM. |
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Intel’s site on the World Wide Web (http://www.intel.com/) provides up-to-date technical information and product support. This information is available 24 hours per day, 7 days per week, providing technical information whenever you need it.
Product documentation is provided online in a variety of web-friendly formats at:
(http://developer.intel.com/)
If you require additional technical support, please contact your field sales representative or local distributor.
Product literature can be ordered from the following Intel literature centers:
Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit |
|
User’s Manual |
October 2007 |
8 |
Order Number: 318476001US |
About This Manual—Intel Core 2 Duo Processor and Intel Q35 Express Chipset
Table 2. |
Intel Literature Centers |
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Location |
Telephone Number |
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U.S. and Canada |
1-800-548-4725 |
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U.S. (from overseas) |
708-296-9333 |
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Europe (U.K.) |
44(0)1793-431155 |
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Germany |
44(0)1793-421333 |
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France |
44(0)1793-421777 |
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Japan (fax only) |
81(0)120-47-88-32 |
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Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit |
October 2007 |
User’s Manual |
Order Number: 318476001US |
9 |
Intel Core 2 Duo Processor and Intel Q35 Express Chipset—Development Kit Hardware Features
This chapter describes the features of the Intel® Q35 Development Kit. These recommendations would largely apply to other designs incorporating Intel® Q35 chipset. This documentation should be used in conjunction with the datasheets, specification updates and platform design guides for the Intel® I/O Controller Hub 9 (ICH9) Family and the Intel® Q35 Express Chipset. Contact your Intel representative for the availability of these documents.
Figure 1 shows overview of the major features present on the development kit board. Refer to next page for system block diagram of the development kit’s motherboard.
Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit |
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User’s Manual |
October 2007 |
10 |
Order Number: 318476001US |
Development Kit Hardware Features—Intel Core 2 Duo Processor and Intel Q35 Express Chipset
Figure 1. |
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Board Features |
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PCI Slot |
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Power Button |
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SPI EEPROM |
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PCI Express |
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x16 Graphics |
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LGA775 Processor |
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Socket |
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Controller Hub |
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SATA Port |
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Intel® Q35 Memory |
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Controller Hub (MCH) |
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2x2 Standard |
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Power Supply |
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2x12 |
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Standard |
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Power Supply |
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2-DIMM per channel DDR2 |
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667/800 (Channel-B) |
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667/800 (Channel-A) |
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This section will document the common features that are applicable to the Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit. Figure 2 shows a simple block diagram of the development kit.
|
Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit |
October 2007 |
User’s Manual |
Order Number: 318476001US |
11 |