VHF MARINE TRANSCEIVER
iCm88
This service manual describes the latest service information for the IC-M88 VHF MARINE TRANSCEIVER at the time of publication.
Model |
Version |
Symbol |
FM I/S |
Battery pack |
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U.S.A. |
USA |
NO |
BP-227 |
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IC-M88 |
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USA-1 |
YES |
BP-227FM |
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S.E. Asia |
SEA |
NO |
BP-227 |
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To upgrade quality, all electrical or mechanical parts and internal circuits are subject to change without notice or obligation.
DANGER
NEVER connect the transceiver to an AC outlet or a DC power supply that uses more than 8.3 V. This will ruin the transceiver.
DO NOT expose the transceiver to rain, snow or liquids.
DO NOT reverse the polarities of the power supply connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW) to the antenna connector. This could damage the transceiverís front end.
ORDERING PARTS
Be sure to include the following four points when ordering replacement parts:
1.10-digit order numbers
2.Component part number and name
3.Equipment model name and unit name
4.Quantity required
<SAMPLE ORDER>
1110002750 |
S.IC TA7S01F |
IC-M88 |
MAIN UNIT |
1 piece |
8210019100 |
2600 Front panel |
IC-M88 |
CHASSIS |
5 pieces |
Addresses are provided on the inside back cover for your convenience.
REPAIR NOTES
1.Make sure the problem is internal before disassembling the transceiver.
2.DO NOT open the transceiver until the transceiver is disconnected from its power source.
3.DO NOT force any of the variable components. Turn them slowly and smoothly.
4.DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.
5.DO NOT keep power ON for a long time when the transceiver is defective.
6.DO NOT transmit power into a signal generator or a sweep generator.
7.ALWAYS connect a 40 dB or 50 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment.
8.READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.
SECTION |
1 |
SPECIFICATIONS |
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SECTION |
2 |
INSIDE VIEWS |
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SECTION |
3 |
DISASSEMBLY INSTRUCTIONS |
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SECTION |
4 |
CIRCUIT DESCRIPTION |
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4 - 1 |
RECEIVER CIRCUITS ................................................................................................... |
4 - 1 |
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4 - 2 |
TRANSMITTER CIRCUITS ............................................................................................ |
4 - 2 |
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4 - 3 |
PLL CIRCUITS................................................................................................................. |
4 - 3 |
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4 - 4 |
POWER SUPPLY CIRCUITS ......................................................................................... |
4 - 3 |
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4 - 5 |
CPU PORT ALLOCATIONS ........................................................................................... |
4 - 4 |
SECTION |
5 |
ADJUSTMENT PROCEDURES |
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5 - 1 |
PREPARATION................................................................................................................ |
5 - 1 |
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5 - 2 |
SOFTWARE ADJUSTMENT ........................................................................................... |
5 - 4 |
SECTION |
6 |
PARTS LIST |
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SECTION |
7 |
MECHANICAL PARTS AND DISASSEMBLY |
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SECTION |
8 |
SEMI-CONDUCTOR INFORMATION |
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SECTION |
9 |
BOARD LAYOUTS |
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9 - 1 |
CHARGER UNIT ............................................................................................................. |
9 - 1 |
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9 - 2 |
VR UNIT .......................................................................................................................... |
9 - 1 |
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9 - 3 |
CONNECTOR UNIT ........................................................................................................ |
9 - 1 |
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9 - 4 |
MAIN UNIT....................................................................................................................... |
9 - 2 |
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9 - 5 |
LOGIC UNIT .................................................................................................................... |
9 - 4 |
SECTION |
10 |
BLOCK DIAGRAM |
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SECTION |
11 |
VOLTAGE DIAGRAM |
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SECTION 1 SPECIFICATIONS
GENERAL
• Frequency coverage |
: TX: 156.025–157.425 MHz, RX: 156.050–163.275 MHz |
[MARINE] |
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TX/RX: 146.000–174.000 MHz |
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[LMR] |
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• Number of free channels |
: 22 channels |
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• Type of emission |
: 16K0G3E (Wide; 25 kHz) |
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[MARINE] |
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16K0F3E (Wide; 25 kHz), 8K50F3E (Narrow; 12.5 kHz) |
[LMR] |
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• Antenna connector |
: SMA (50 Ω) |
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• Power supply requirement |
: BP-227/FM (7.2 V DC, negative ground) |
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• Current drain (approx.) |
: Transmit |
at High (5.0 W) |
1.6 A |
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at Middle (3.0 W) |
1.2 A |
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at Low1 (1.0 W) |
0.7 A |
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Receive |
at maximum audio |
200 mA |
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at stand-by |
Less than 120 mA |
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• Usable temperature range |
: –20˚C to +60˚C; –4˚F to +140˚F |
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[MARINE] |
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–30˚C to +60˚C; –22˚F to +140˚F |
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[LMR] |
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• Dimensions (projections not included) : 62(W) × 97(H) × 39(D) mm; 27⁄16(W) × 313⁄16(H) × 117⁄32(D) in. |
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• Weight (with antenna, BP-227/FM) |
: 280 g; 97⁄8 oz (approx.) |
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TRANSMITTER
• RF output power (with BP-227/FM) |
: 5 W / 3 W / 1 W (High / Middle / Low) |
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• Modulation system |
: Variable reactance frequency modulation |
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• Maximum frequency deviation |
: ±5.0 kHz (Wide) |
[MARINE] |
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±5.0 kHz (Wide), ±2.5 kHz (Narrow) |
[LMR] |
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• Frequency error |
: ±5.0 ppm |
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• Spurious emissions |
: –70 dBc |
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• Adjacent channel power |
: 70 dB |
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[MARINE] |
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70 dB (Wide), 60 dB (Narrow) |
[LMR] |
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• Audio harmonic distortion |
: 10% at 60% deviation |
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• FM Hum and noise |
: 40 dB |
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[MARINE] |
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40 dB (Wide), 34 dB (Narrow) |
[LMR] |
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• Limiting charact modulation |
: 60–100% of maximum deviation |
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• Ext. microphone connector |
: 9-pin multi connector/2.2 kΩ |
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RECEIVER |
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• Receive system |
: Double conversion superheterodyne system |
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• Intermediate frequencies |
: 1st |
31.05 MHz |
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2nd |
450 kHz |
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• Sensitivity |
: 0.25 µV typical at 12 dB SINAD |
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• Squelch sensitivity |
: 0.35 µV typical at threshold |
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• Adjacent channel selectivity |
: 70 dB typical |
[MARINE] |
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70 dB typical (Wide), 60 dB typical (Narrow) |
[LMR] |
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• Spurious response rejection |
: 70 dB typical |
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• Intermodulation rejection ratio |
: 70 dB typical |
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• Hum and noise |
: 40 dB |
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[MARINE] |
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40 dB (Wide), 34 dB (Narrow) |
[LMR] |
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• Audio output power (at 7.2 V DC) |
: 350 mW typical at 10% distortion with an 8 Ω load |
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• Ext. speaker connector |
: 9-pin multi connector/8 Ω |
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Specifications are measured in accordance with TIA/EIA-603.
All stated specifications are subject to change without notice or obligation.
1 - 1
Channel No. |
Frequency (MHz) |
Channel No. |
Frequency (MHz) |
Channel No. |
Frequency (MHz) |
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USA |
INT |
CAN |
Transmit |
Receive |
USA |
INT |
CAN |
Transmit |
Receive |
USA |
INT |
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Transmit |
Receive |
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01 |
01 |
156.050 |
160.650 |
21A |
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21A |
157.050 |
157.050 |
73 |
73 |
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156.675 |
156.675 |
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01A |
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156.050 |
156.050 |
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22 |
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157.100 |
161.700 |
74 |
74 |
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156.725 |
156.725 |
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02 |
02 |
156.100 |
160.700 |
22A |
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22A |
157.100 |
157.100 |
77*1 |
77 |
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156.875 |
156.875 |
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03 |
03 |
156.150 |
160.750 |
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23 |
23 |
157.150 |
161.750 |
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78 |
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156.925 |
161.525 |
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03A |
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156.150 |
156.150 |
23A |
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157.150 |
157.150 |
78A |
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156.925 |
156.925 |
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04 |
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156.200 |
160.800 |
24 |
24 |
24 |
157.200 |
161.800 |
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79 |
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156.975 |
161.575 |
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04A |
156.200 |
156.200 |
25 |
25 |
25 |
157.250 |
161.850 |
79A |
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156.975 |
156.975 |
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05 |
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156.250 |
160.850 |
26 |
26 |
26 |
157.300 |
161.900 |
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80 |
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157.025 |
161.625 |
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05A |
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05A |
156.250 |
156.250 |
27 |
27 |
27 |
157.350 |
161.950 |
80A |
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157.025 |
157.025 |
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06 |
06 |
06 |
156.300 |
156.300 |
28 |
28 |
28 |
157.400 |
162.000 |
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81 |
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157.075 |
161.675 |
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07 |
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156.350 |
160.950 |
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60 |
60 |
156.025 |
160.625 |
81A |
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157.075 |
157.075 |
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07A |
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07A |
156.350 |
156.350 |
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61 |
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156.075 |
160.675 |
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82 |
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157.125 |
161.725 |
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08 |
08 |
08 |
156.400 |
156.400 |
61A |
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61A |
156.075 |
156.075 |
82A |
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157.125 |
157.125 |
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09 |
09 |
09 |
156.450 |
156.450 |
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62 |
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156.125 |
160.725 |
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83 |
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157.175 |
161.775 |
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10 |
10 |
10 |
156.500 |
156.500 |
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62A |
156.125 |
156.125 |
83A |
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157.175 |
157.175 |
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11 |
11 |
11 |
156.550 |
156.550 |
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63 |
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156.175 |
160.775 |
84 |
84 |
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157.225 |
161.825 |
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12 |
12 |
12 |
156.600 |
156.600 |
63A |
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156.175 |
156.175 |
84A |
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157.225 |
157.225 |
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13*2 |
13 |
13*1 |
156.650 |
156.650 |
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64 |
64 |
156.225 |
160.825 |
85 |
85 |
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157.275 |
161.875 |
14 |
14 |
14 |
156.700 |
156.700 |
64A |
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64A |
156.225 |
156.225 |
85A |
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157.275 |
157.275 |
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15*2 |
15*1 |
15*1 |
156.750 |
156.750 |
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65 |
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156.275 |
160.875 |
86 |
86 |
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157.325 |
161.925 |
16 |
16 |
16 |
156.800 |
156.800 |
65A |
65A |
65A |
156.275 |
156.275 |
86A |
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157.325 |
157.325 |
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17*1 |
17 |
17*1 |
156.850 |
156.850 |
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66 |
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156.325 |
160.925 |
87 |
87 |
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157.375 |
161.975 |
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18 |
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156.900 |
161.500 |
66A |
66A |
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156.325 |
156.325 |
87A |
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157.375 |
157.375 |
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18A |
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18A |
156.900 |
156.900 |
67*2 |
67 |
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156.375 |
156.375 |
88 |
88 |
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157.425 |
162.025 |
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19 |
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156.950 |
161.550 |
68 |
68 |
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156.425 |
156.425 |
88A |
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157.425 |
157.425 |
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19A |
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19A |
156.950 |
156.950 |
69 |
69 |
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156.475 |
156.475 |
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20 |
20 |
20*1 |
157.000 |
161.600 |
70*3 |
70*3 |
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156.525 |
156.525 |
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20A |
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157.000 |
157.000 |
71 |
71 |
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156.575 |
156.575 |
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21 |
21 |
157.050 |
161.650 |
72 |
72 |
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156.625 |
156.625 |
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*1 Low power only, *2 Momentary high power, *3 Receive only
NOTE: Channels 3, 21, 23, 61, 64, 81, 82 and 83 CANNOT be used by the general public in USA waters.
WX CHANNEL LIST
Weather |
Frequency (MHz) |
Weather |
Frequency (MHz) |
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channel |
Transmit |
Receive |
channel |
Transmit |
Receive |
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WX01 |
Receive only |
162.550 |
WX06 |
Receive only |
162.500 |
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WX02 |
Receive only |
162.400 |
WX07 |
Receive only |
162.525 |
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WX03 |
Receive only |
162.475 |
WX08 |
Receive only |
161.650 |
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WX04 |
Receive only |
162.425 |
WX09 |
Receive only |
161.775 |
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WX05 |
Receive only |
162.450 |
WX10 |
Receive only |
163.275 |
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1 - 2
SECTION 2 INSIDE VIEWS
• LOGIC UNIT
Bottom view
*: Located in another side of this point.
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AF mute circuit |
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Q441* |
: 2SC4116 |
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Q442* |
: CPH3403 |
IN/EXT microphone switch |
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Q443 |
: CPH3403 |
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Q444 |
: DTC144EU |
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(Q461, Q462: UN911H) |
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EEPROM |
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Microphone amplifier |
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(IC591*: HN58X2416TI) |
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(IC471: NJM2904V) |
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CPU
AF mute (IC661: µPD780316GC-511-9EB) (IC481: TC4W66FU)
S5V regulator (Q561: 2SA1588)
M5V regulator
Q551: 2SB1132
Q552: XP6501
Q553: DTC144EU
• MAIN UNIT
Top view |
Bottom view |
Antenna switching circuit
D131, D151: 1SV307
D152: MA77
RF amplifier (Q165: 3SK294)
Power amplifier (Q111: RD07MVS1)
Pre-drive amplifier (Q101: RD01MUS1)
T5V regulator |
(Q323: 2SA1588) |
R5V regulator |
(Q322: 2SA1588) |
V5V regulator (Q321: 2SA1588)
VCO circuit
1st Mixer (Q191: 3SK299)
AF mute
(IC281: TC4W66FU)
APC control (IC141: TA75S01F)
Bandpass filter (FI211: FL-355)
PLL IC
(IC1: MB15A02PFV)
Reference frequency |
crystal |
(X1: CR664A; |
15.300 MHz) |
FM IF IC (IC231: TA31136FN)
IF amplifier (Q211: 2SC4215)
D/A converter (IC251:
M62363FP-650C)
2 - 1
SECTION 3 DISASSEMBLY INSTRUCTIONS
1. Removing the chassis panel
q Remove nut A.
w Unscrew 2 screws B (2 × 8 mm, black) and 3 screws C (2 × 4 mm, black) from the chassis.
e Take off the chassis in the direction of the arrow.
NOTE: * Tighten the screws in order of a number (q–y) when assembling.
C
w
q
A
C
y B e
r
Chassis
t C
2. Removing the LOGIC unit.
q Unplug the cable from J281 on the MAIN unit to separate the LOGIC unit
wSeparate the front panel from the chassis in the direction of the arrow.
eUnsolder 2 leads of the speaker and connector unit (9 points).
rUnscrew 3 screws D (2 × 4 mm, silver) to separate the front panel.
NOTE: * Tighten the screws in order of a number (z–c) when assembling.
3. Removing the MAIN unit
qUnsolder 4 leads of contact spring and antenna connector (1 point).
wUnscrew 6 screws D (2 × 4 mm, silver) to separate the chassis.
NOTE: * Tighten the screws in order of a number (q–y) when assembling.
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D |
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E |
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z |
c |
w |
t |
r |
J281 |
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Chassis |
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VR unit |
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W801 |
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J281 |
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Unsolder
(A contact spring
and antenna connector)
Unsolder
(A SP and connector unit)
Front panel |
LOGIC UNIT |
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MAIN UNIT |
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x |
e |
y |
q |
D |
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E |
3 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1-1 ANTENNA SWITCHING CIRCUIT (MAIN UNIT)
The antenna switching circuit functions as a low-pass filter while receiving and as resonator circuit while transmitting. The circuit does not allow transmit signals to enter receiver circuits.
Received signals from the antenna connector pass through the low-pass filter (L131, L132, C131–C136) and antenna switching circuit (D151, D152). The filtered signals are then applied to the RF amplifier circuit (Q165).
4-1-2 RF AND 1ST MIXER CIRCUITS (MAIN UNIT)
The 1st mixer circuit converts the received signals to a fixed frequency of the 1st IF signal with a PLL output frequency. By changing the PLL frequency, only the desired frequency will be passed through a pair of crystal filters at the next stage of the 1st mixer.
The signals from the antenna switching circuit are passed through the 2-stage bandpass filters (D154, D155, L154, L155) and amplified at the RF amplifier (Q165). The amplified signals are passed through another 2-stage bandpass filters (D181, D182, L181, L182), and then applied to the 1st mixer circuit (Q199).
The filtered signals are mixed at the 1st mixer (Q199) with a 1st LO signal coming from the PLL circuit to produce a 31.05 MHz 1st IF signal. The 1st IF signal is passed through a pair of crystal filter (FI211) and is then amplified at the IF amplifier (Q211).
4-1-3 2ND IF AND DEMODULATOR CIRCUITS (MAIN UNIT)
The 2nd mixer circuit converts the 1st IF signal to a 2nd IF signal. A double conversion superheterodyne system (which converts receive signal twice) improves the image rejection and obtain stable receiver gain.
• 2ND IF AND DEMODULATOR CIRCUITS
The 1st IF signal is applied to a 2nd mixer section of the FM IF IC (IC231, pin 16). The signal is then mixed with a 2nd LO signal for conversion into a 450 kHz 2nd IF signal.
IC231 contains the 2nd mixer, limiter amplifier, quadrature detector and active filter circuits. A 30.6 MHz 2nd LO signal is produced at the PLL circuit using the reference frequency.
The 2nd IF signal from the 2nd mixer (IC231, pin 3) passes through ceramic filters (FI231, FI232) to remove unwanted heterodyned frequencies. It is then amplified at the limiter amplifier section (IC231, pin 5) and applied to the quadrature detector section (IC231, pins 10 and 11) to demodulate the 2nd IF signal into AF signals.
4-1-4 AF CIRCUIT (MAIN AND LOGIC UNITS)
AF signals from the FM IF IC (IC231, pin 9) are fed to the analog switch (IC282).
The AF signals (detected signals) passes through the AF mute switch (IC281A, pins 2 and 1) via “DET” signal, and are then applied to the analog switch (IC282, pin 1). The signals are then applied to the low-pass filter (IC261B, C266, C267, R270–R272).
The filtered AF signals are applied to and adjusted audio level at the [VOL] control (VR unit; R801) via the “VOLIN” signal. The level controlled signals are passed through the AF mute switch (LOGIC unit; Q411) which is controlled by “AFMS” signal from the CPU (IC661, pin 84). The passed signals are applied to the AF power amplifier (IC421, pin 4), and then output to the internal speaker or [EXT SP] jack after being passed through the de-emphasis circuit (R411, C413) to obtain the –6 dB/octave frequency characteristics
R240 R241
"SQCON" signal to the D/A convertor IC (IC251, pin 2)
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Q231 |
2nd IF filters |
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Q232 |
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450 kHz |
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W/N |
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C238 |
C239 |
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SW |
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8 |
R239 |
7 |
5 |
Fl232 Fl231 |
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Noise |
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Active |
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detector |
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filter |
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IF amp. |
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FM |
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"SQLOUT" signal to the D/A |
detector |
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Noise |
convertor IC (IC251, pin 1) |
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RSSI |
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comp. |
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C242 |
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9 |
10 |
11 |
12 |
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AF signal "DET" |
R242 |
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C232 |
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C244 |
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C243 |
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R231 |
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30.6 MHz |
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2 |
17 |
16 |
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3 |
2 Q221 |
PLL IC |
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IC1 |
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2nd |
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Mixer |
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X1 |
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15.3 MHz |
IC231 TA31136FN(D)
14 16
"IF" (1st IF signal: 31.05 MHz) from RF unit, Q211
"NOISV" signal to the CPU (pin 32)
R232 |
"RSSIV" signal to the CPU (pin 33) |
R5V
X231
450 kHz
4 - 1
4-1-5 SQUELCH CIRCUIT (MAIN AND LOGIC UNITS)
The noise squelch circuit cuts out AF signals when no RF signals are received. By detecting noise components in the AF signals, the squelch circuit switches the AF mute switch.
A portion of the AF signals divided by C242 from the FM IF IC (IC231, pin 9) are applied to the D/A converter (IC251, pin 2) to adjust amplitude. The signals from the D/A converter (IC251, pin 1) are applied to the active filter section (IC231, pin 8, R239–R241, C237, C238). The active filter section amplifies and filters noise components. The filtered signals are applied to the noise detector section and output from IC231 (pin 14) as the “NOISV” signal.
The “NOISV” signal from IC231 (pin 14) is applied to the CPU (LOGIC unit; IC611, pin 32). The CPU compares the set squelch level voltage and “NOISV” signal voltage to control the squelch output.
4-2-1 MICROPHONE AMPLIFIER CIRCUIT (LOGIC AND MAIN UNITS)
The microphone amplifier circuit amplifies audio signals with +6 dB/octave pre-emphasis characteristics from the microphone to a level needed for the modulation circuit.
• In case of the internal microphone
The AF signals from the internal microphone (MC461) is applied to the microphone amplifier (IC471a, pin 6) via the “INMIC” signal.
• In case of external microphone
The AF signals from the external microphone (CP458) is applied to the microphone amplifier (IC471a, pin 6) via the “EXTMIC” signal.
The amplified signals are passed through the pre-emphasis circuit (R463, C463) and are then applied to the AF mute switch (IC481a, pin 1) via the “MICO” signal after being passed through the another microphone amplifier (IC471b, pins 2 and 1).
The AF signals are amplified again at the limiter-amplifier (IC491a, pin 2) and then passed through the low-pass filter (IC491b, pins 6 and 7). The filtered audio passes through the analog swtich (MAIN unit; IC251, pins 4 and 3), and is then applied to the MAIN unit as the “MOCON” signal.
4-2-2 MODULATION CIRCUIT (MAIN UNIT)
The modulation circuit modulates the VCO oscillating signal (RF signal) using the microphone audio signals.
The audio signals “MOCON” change the reactance of D39 to modulate an oscillated signal at the TX VCO circuit (Q51, D35–D38, L34, L51, C32, C33, C52–C54). The oscillated signal is amplified at the buffer-amplifiers (Q61, Q62).
4-2-3 PRE-DRIVE/POWER AMPLIFIER CIRCUITS (MAIN UNIT)
The signal from the VCO circuit passes through the transmit/receive switching circuit (D91, D92) and is applied to the buffer-amplifier (Q91). The amplified signal is amplified by the pre-driver (Q101) and the power amplifier (Q101) to obtain 5 W of RF power (at 7.2 V). The amplified signal passes through the antenna switching circuit (D131), and low-pass filter (L131, L132, C131–C136) and is then applied to the antenna connector.
The bias current of the buffer amplifier (Q91), pre-driver (Q101) and power amplifier (Q111) is controlled by the APC circuit to stabilize the output power.
4-2-4 APC CIRCUIT (MAIN UNIT)
The APC circuit provides stable output power from the power amplifier even when the input voltage or temperature changes, and, selects HIGH, MIDDLE, LOW or EXTRA LOW output power. The APC circuit consists of a power detector and APC control circuits.
• POWER DETECTOR CIRCUIT (MAIN UNIT)
The power detector circuit (D132) detects the transmit output power level and converts it to DC voltage as the “TDETV” signal. The detected signal is applied to the APC control circuit.
• APC CONTROL CIRCUIT (MAIN AND LOGIC UNITS)
The “TDETV” signal from the power detector circuit is applied to the CPU (LOGIC unit; IC661, pin 31) to control the input voltage of the buffer amplifier (Q91), pre-driver (Q101) and power amplifier (Q111). When the output power changes, the CPU (LOGIC unit; IC661) outputs APC control signal to the D/A converter (IC190). And then “T1CON” signal from the D/A converter controls the APC controller (IC141) to provide stable output power.
• APC CIRCUIT |
VCC |
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T5V |
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S5V |
"TXMS" signal from the expander IC (IC341, pin 12)
"T1CON" signal from the D/A convertor IC (IC251, pin 14)
antenna
RF signal |
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Q91 |
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Q101 |
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Q111 |
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D131 |
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from PLL |
Buffer |
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Pre-drive |
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Power |
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ANT |
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LPF |
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amp. |
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amp. |
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amp. |
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SW |
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3 |
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Power detector |
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circuit (D132) |
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Q141 |
IC141 |
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1 |
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APC control circuit
"TDETV" to the CPU (LOGIC unit; IC661, pin 31)
4 - 2
4-3 PLL CIRCUIT (MAIN UNIT)
4-3-1 GENERAL
The PLL circuit provides stable oscillation of the transmit frequency and receive 1st LO frequency. The PLL output compares the phase of the divided VCO frequency to the reference frequency. The PLL output frequency is controlled by the divided ratio (N-data) of a programmable divider. IC1 is a PLL IC which controls both VCO circuit for TX and RX.
The PLL circuit, using a one chip PLL IC (IC1), directly generates the transmit frequency and receive 1st IF frequency with VCOs. The PLL sets the divided ratio based on serial data from the CPU on the LOGIC unit and compares the phases of VCO signals with the reference oscillator frequency. The PLL IC detects the out-of-step phase and output from the pin 6 for TX and RX. The reference frequency (15.3 MHz) is oscillated at X1.
4-3-2 TX AND RX LOOP CIRCUITS (MAIN UNIT)
The generated signal at the TX-VCO circuit (Q51, D35 –D38, L34, L51, C32, C33, C52–C54) or RX-VCO (Q41, D31–D34, L32, L41, C31, C41–C43) enters the PLL IC (IC1, pin 8) and is divided at the programmable divider section and is then applied to the phase detector section.
The phase detector compares the input signal with a reference frequency, and then outputs the out-of-phase signal (pulse-type signal) from pin 6.
The pulse-type signal is converted into DC voltage (lock voltage) at the loop filter (R17–R19, C16–C19), and then applied to varactor diodes (TX; D35–D38, RX; D31–D34) of the TX-VCO and RX-VCO to stabilize the oscillated frequency.
4-3-3 TX AND RX VCO CIRCUITS (MAIN UNIT)
The VCO circuit from Q41 (RX) and Q5 (TX) are buffer amplified at the Q61 and Q62, and then sent to the TX/RX swtich (D91, D92). The receive LO signal is applied to the 1st mixer circuit (Q191) through an attenuator (L203, R203 –R206, C202, C203), and the transmit signal is applied to the buffer amplifier (Q91). A portion of the VCO output is reapplied to the PLL IC (IC1, pin 8) via the Q71.
• PLL CIRCUIT
VOLTAGE LINES
LINE |
DESCRIPTION |
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HV |
The voltage from the attached battery pack. |
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The same voltage as the HV line (battery |
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voltage) which is controlled by the power switch |
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(VR unit; [OFF/VOL] control). |
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VCC |
The output voltage is applied to the pre-drive |
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(MAIN unit; Q101), power amplifier (MAIN unit; |
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Q111), CPU5V and M5V regulator circuits |
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(LOGIC unit; IC551 and Q551–Q553). |
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Common 5 V converted from the VCC line by the |
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CPU5V regulator circuit (LOGIC unit; IC551). |
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CPU5V |
The output voltage is applied to the CPU (LOGIC |
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unit; IC661), RESET circuit (LOGIC unit; IC581), |
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etc. |
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Common 5V converted from the VCC line by the |
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M5V regulator circuit (LOGIC unit; Q551–Q553). |
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M5V |
The output voltage is applied to R5V, T5V, V5V and |
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S5V regulator circuits (LOGIC unit; Q322, Q323, |
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Q321 and Q561). |
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Receive 5V converted from the M5V line by the |
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R5V regulator circuit (MAIN unit; Q322). |
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R5V |
The regulated voltage is applied to the 1st mixer |
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circuit (MAIN unit; Q191), RF and IF amplifiers |
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(MAIN unit; Q165, Q211). |
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Transmit 5V converted from the M5V line by the |
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T5V |
T5V regulator circuit (MAIN unit; Q222). |
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The regulated voltage is applied to the buffer |
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amplifier (MAIN unit; Q91). |
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Common 5V converted from the M5V line by |
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V5V |
the V5V regulator circuit (MAIN unit; Q321). |
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The regulated voltage is applied to the ripple |
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filter circuit (Q47). |
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Common 5V converted from the M5V line by the |
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S5V regulator circuit (LOGIC unit; Q561). |
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S5V |
The regulated voltage is applied to the microphone |
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amplifier (LOGIC unit; IC471), limit amplifier |
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(LOGIC unit; IC491), LCD back light (LOGIC unit; |
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DS651–DS654), etc. |
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S5V
RX VCO
Q81
Q82
VCOS |
Q41, D31 D34 |
Buffer |
D91 to transmitter circuit |
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Buffer |
Q62 |
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to the 1st mixer circuit |
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TX VCO |
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VCO SWITCH |
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Q61 |
Buffer |
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D92 |
FM |
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Q51, D35 D38 |
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MOD. |
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Q71 |
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D39 |
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Loop |
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IC1 MB15A02PFV |
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LPF |
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filter |
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5 |
Phase |
Programmable |
Prescaler |
8 |
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detector |
counter |
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"2nd LO" signal (30.6 MHz) |
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11 |
PLSTBO |
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to the FM IF IC (IC231, pin 2) |
2 |
Programmable |
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Shift register |
10 |
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2 |
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divider |
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9 |
SDATAO |
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Q221 |
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SCLKO |
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1 |
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X1 |
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15.3 MHz |
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4 - 3
4-5-1 CPU (LOGIC UNIT; IC661)
Pin |
Port |
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Description |
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number |
name |
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1 |
BEEP |
Outputs beep audio signals. |
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2 |
VSSTB |
Outputs strobe signals for the scrambler |
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IC (MAIN unit; IC381, pin 10). |
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3 |
EXSTB |
Outputs strobe signals |
for the |
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expander IC (MAIN unit; IC341, pin 1). |
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4 |
DASTB |
Outputs strobe |
signals for |
the D/A |
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converter (MAIN unit; IC251, pin 6). |
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5 |
PLSTB |
Outputs strobe signals for the PLL IC |
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(MAIN unit; IC1, pin 11). |
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6 |
ERXDI |
Input port for cloning signals. |
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7 |
ETXDO |
Outputs cloning signals. |
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10 |
SDATA |
Outputs serial data for PLL, scrambler |
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ICs, etc. |
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11 |
SCLK |
Outputs serial clock for PLL, |
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scrambler ICs, etc. |
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12 |
ESCK |
Outputs clock signal for the EEPROM |
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(IC591, pin 6). |
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13 |
ESDA |
I/O port for EEPROM data signal |
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(IC591, pin 5). |
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17 |
CSIFT |
Outputs CPU clock shift signal. |
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High : While clock is shifted. |
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27 |
WDECV |
Input port for the WX tone detection. |
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28 |
WETIN |
Input port for the transceiver’s internal |
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inundation detection. |
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29 |
EXTSV |
Input port |
for the external |
terminal |
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connecting detection. |
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30 |
BATTV |
Input port |
for |
the battery |
voltage |
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detection. |
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31 |
TDETV |
Input port |
for |
transmit RF level |
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detection. |
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32 |
NOISV |
Input port for noise level detection. |
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33 |
RSSIV |
Input port |
for |
RSSI voltage level |
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detection. |
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34 |
LOINV |
Input port for VCO lock voltage level |
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detection. |
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35 |
TEMPV |
Input port for the transceiver’s internal |
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temperature detection. |
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36 |
CDECV |
Input port for CTCSS/DTCS detection. |
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38 |
ATIS |
Outputs ATIS wave form. |
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46–48 |
COM0– |
Output LCD common signals |
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COM2 |
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51–70 |
SEG0– |
Output LCD segment signals. |
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SEG19 |
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75 |
CONT1 |
Output LCD contrast control signals. |
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76 |
CONT2 |
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77 |
LEDS1 |
Output LCD and key’s back light |
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78 |
LEDS2 |
dimmer control signal. |
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Pin |
Port |
Description |
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number |
name |
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STXMS |
Outputs scrambler mute signal for the |
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79 |
AF mute circuit (IC481, pin 3). |
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Low : While scrambler is muting. |
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Outputs mic mute signal for the AF |
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80 |
MICMS |
mute circuit (IC481, pin 7). |
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Low : While the microphone is |
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muting. |
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Outputs the internal speaker control |
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81 |
ISPMS |
signal. |
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High : While the speaker is muting. |
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82 |
LDTFS |
Outputs DTCS’s low-pass filter cut-off |
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frequency control signal. |
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83 |
W/NS |
Outputs Wide/Narrow control signal. |
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high : While Narrow is selected. |
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AFMS |
Outputs the AF mute circuit control |
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84 |
signal. |
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High : The AF mute circuit is ON. |
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AFVS |
Outputs AF amplifier’s power supply |
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85 |
control signal. |
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High : The AF amplifier is ON. |
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M5VS |
Outputs M5V power supply control |
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86 |
signal. |
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Low : The common 5V is supplied. |
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S5VS |
Outputs S5V power supply control |
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87 |
signal. |
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Low : The common 5V is supplied. |
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Outputs V5V power supply control |
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88 |
V5VS |
signal. |
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Low : The common 5V is supplied. |
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R5VS |
Outputs R5V power supply control |
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89 |
signal. |
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Low : While receiving. |
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T5VS |
Outputs T5V power supply control |
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90 |
signal. |
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Low : While transmitting. |
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98 |
CENC1 |
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99 |
CENC2 |
Output DTCS/CTCSS wave form. |
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100 |
CENC3 |
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102 |
PTTIN |
Input port for [PTT] swtich detection. |
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High : While [PTT] switch is pushed. |
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Input port for HM-138 (optional |
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speaker-microphone)’s [PTT] swtich |
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103 |
EPTTIN |
detection. |
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Low : While HM-138’s [PTT] switch |
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is pushed. |
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BTYPE |
Input port for the connecting battery |
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104 |
type detection. |
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Low : While using alkaline cells. |
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109 |
SQL |
Input port for the [SQL] key. |
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Low : While [SQL] key is pushed. |
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110 |
UP |
Input port for the [UP] key. |
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Low : While [UP] key is pushed. |
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4 - 4
CPU–Continued
Pin |
Port |
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Description |
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number |
name |
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111 |
DOWN |
Input port for the [DOWN] key. |
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Low |
: While [DOWN] key is pushed. |
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112 |
CH/WX |
Input port for the [CH/WX] key. |
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Low |
: While [CH/WX] key is pushed. |
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113 |
16/9 |
Input port for the [16/9] key. |
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Low |
: While [16/9] key is pushed. |
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114 |
SCAN |
Input port for the [SCAN] key. |
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Low |
: While [SCAN] key is pushed. |
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115 |
H/L |
Input port for the [H/L] key. |
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Low |
: While [H/L] key is pushed. |
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119 |
UNLK |
Input port for the PLL unlock signal. |
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High : PLL lock voltage is unlocked. |
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4-5-2 EXPANDER IC (MAIN UNIT; IC341)
Pin |
Port |
Description |
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number |
name |
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Outputs the AF mute switch (IC281, |
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5 |
SRXMS |
pin 3) control signal. |
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Low : While the scrambler decording |
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signal is muted. |
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Outputs the AF mute swtich (IC281, |
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6 |
DETMS |
pin 7) control signal.signal. |
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Low : While AF signal is muted. |
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Outputs the scrambler IC’s clock shift |
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7 |
CKSIS |
control signal. |
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High : While the clock is shifted. |
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Outputs the RF attenuator control |
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11 |
ATTS |
signal. |
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High : While attenuator is ON. |
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Outputs the TX mute swtich (Q141) |
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12 |
TXMS |
control signal. |
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Low : While receiving. |
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13 |
VCOS |
Outputs the TX/RX VCO control |
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signal. |
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4-5-3 D/A CONVERTOR IC (MAIN UNIT; IC251)
Pin |
Port |
Description |
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number |
name |
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2 |
SQCON |
Outputs squelch level control signal. |
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3 |
MOCON |
Outputs modulatin level control signal. |
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10 |
DTCON |
Outputs DTCS modulation balance |
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control signal. |
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11 |
FRCON |
Outputs reference |
frequency |
level |
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control signal. |
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14 |
T1CON |
Outputs bandpass |
filter1 tuned |
and |
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transmitting power control signals. |
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15 |
T2CON |
Outputs bandpass filter2 tuned signal. |
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22 |
T3CON |
Outputs bandpass filter3 tuned signal. |
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23 |
T4CON |
Outputs bandpass filter4 tuned signal. |
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4 - 5